blob: 671054d9befa9c1b56dd291e058cd6a7f8c4bf97 [file] [log] [blame]
Peng Fan5e80d5a2018-10-18 14:28:30 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
Simon Glass9bc15642020-02-03 07:36:16 -070010#include <malloc.h>
Peng Fan5e80d5a2018-10-18 14:28:30 +020011#include <asm/arch/sci/sci.h>
12#include <asm/arch/clock.h>
13#include <dt-bindings/clock/imx8qxp-clock.h>
14#include <dt-bindings/soc/imx_rsrc.h>
15#include <misc.h>
16
Peng Fan6a8e5f92019-03-05 02:32:33 +000017#include "clk-imx8.h"
Peng Fan5e80d5a2018-10-18 14:28:30 +020018
Peng Fan6a8e5f92019-03-05 02:32:33 +000019__weak ulong imx8_clk_get_rate(struct clk *clk)
Peng Fan5e80d5a2018-10-18 14:28:30 +020020{
Peng Fan6a8e5f92019-03-05 02:32:33 +000021 return 0;
Peng Fan5e80d5a2018-10-18 14:28:30 +020022}
23
Peng Fan6a8e5f92019-03-05 02:32:33 +000024__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
Peng Fan5e80d5a2018-10-18 14:28:30 +020025{
Peng Fan6a8e5f92019-03-05 02:32:33 +000026 return 0;
Peng Fan5e80d5a2018-10-18 14:28:30 +020027}
28
Peng Fan6a8e5f92019-03-05 02:32:33 +000029__weak int __imx8_clk_enable(struct clk *clk, bool enable)
Peng Fan5e80d5a2018-10-18 14:28:30 +020030{
Peng Fan6a8e5f92019-03-05 02:32:33 +000031 return -ENOTSUPP;
Peng Fan5e80d5a2018-10-18 14:28:30 +020032}
33
34static int imx8_clk_disable(struct clk *clk)
35{
36 return __imx8_clk_enable(clk, 0);
37}
38
39static int imx8_clk_enable(struct clk *clk)
40{
41 return __imx8_clk_enable(clk, 1);
42}
43
44#if CONFIG_IS_ENABLED(CMD_CLK)
45int soc_clk_dump(void)
46{
47 struct udevice *dev;
48 struct clk clk;
49 unsigned long rate;
50 int i, ret;
51
52 ret = uclass_get_device_by_driver(UCLASS_CLK,
53 DM_GET_DRIVER(imx8_clk), &dev);
54 if (ret)
55 return ret;
56
57 printf("Clk\t\tHz\n");
58
Peng Fan6a8e5f92019-03-05 02:32:33 +000059 for (i = 0; i < num_clks; i++) {
Peng Fan5e80d5a2018-10-18 14:28:30 +020060 clk.id = imx8_clk_names[i].id;
61 ret = clk_request(dev, &clk);
62 if (ret < 0) {
63 debug("%s clk_request() failed: %d\n", __func__, ret);
64 continue;
65 }
66
67 ret = clk_get_rate(&clk);
68 rate = ret;
69
70 clk_free(&clk);
71
72 if (ret == -ENOTSUPP) {
73 printf("clk ID %lu not supported yet\n",
74 imx8_clk_names[i].id);
75 continue;
76 }
77 if (ret < 0) {
78 printf("%s %lu: get_rate err: %d\n",
79 __func__, imx8_clk_names[i].id, ret);
80 continue;
81 }
82
83 printf("%s(%3lu):\t%lu\n",
84 imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
85 }
86
87 return 0;
88}
89#endif
90
91static struct clk_ops imx8_clk_ops = {
92 .set_rate = imx8_clk_set_rate,
93 .get_rate = imx8_clk_get_rate,
94 .enable = imx8_clk_enable,
95 .disable = imx8_clk_disable,
96};
97
98static int imx8_clk_probe(struct udevice *dev)
99{
100 return 0;
101}
102
103static const struct udevice_id imx8_clk_ids[] = {
104 { .compatible = "fsl,imx8qxp-clk" },
Peng Fan9a0dc912019-03-05 02:32:35 +0000105 { .compatible = "fsl,imx8qm-clk" },
Peng Fan5e80d5a2018-10-18 14:28:30 +0200106 { },
107};
108
109U_BOOT_DRIVER(imx8_clk) = {
110 .name = "clk_imx8",
111 .id = UCLASS_CLK,
112 .of_match = imx8_clk_ids,
113 .ops = &imx8_clk_ops,
114 .probe = imx8_clk_probe,
115 .flags = DM_FLAG_PRE_RELOC,
116};