blob: 85d56f6082bc4221c4359ca6cf7aee68051a221e [file] [log] [blame]
Marek Vasut5ff05292020-01-24 18:39:16 +01001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6#include <common.h>
7#include <adc.h>
8#include <asm/arch/stm32.h>
9#include <asm/arch/sys_proto.h>
10#include <asm/gpio.h>
11#include <asm/io.h>
12#include <bootm.h>
13#include <clk.h>
14#include <config.h>
15#include <dm.h>
16#include <dm/device.h>
17#include <dm/uclass.h>
18#include <env.h>
19#include <env_internal.h>
20#include <g_dnl.h>
21#include <generic-phy.h>
22#include <hang.h>
23#include <i2c.h>
24#include <i2c_eeprom.h>
25#include <init.h>
26#include <led.h>
27#include <memalign.h>
28#include <misc.h>
29#include <mtd.h>
30#include <mtd_node.h>
31#include <netdev.h>
32#include <phy.h>
33#include <power/regulator.h>
34#include <remoteproc.h>
35#include <reset.h>
36#include <syscon.h>
37#include <usb.h>
38#include <usb/dwc2_udc.h>
39#include <watchdog.h>
40
41/* SYSCFG registers */
42#define SYSCFG_BOOTR 0x00
43#define SYSCFG_PMCSETR 0x04
44#define SYSCFG_IOCTRLSETR 0x18
45#define SYSCFG_ICNR 0x1C
46#define SYSCFG_CMPCR 0x20
47#define SYSCFG_CMPENSETR 0x24
48#define SYSCFG_PMCCLRR 0x44
49
50#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
51#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
52
53#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
54#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
55#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
56#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
57#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
58
59#define SYSCFG_CMPCR_SW_CTRL BIT(1)
60#define SYSCFG_CMPCR_READY BIT(8)
61
62#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
63
64#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
65#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
66
67#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
68
69#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
70#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
71#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
72#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
73
74/*
75 * Get a global data pointer
76 */
77DECLARE_GLOBAL_DATA_PTR;
78
79int setup_mac_address(void)
80{
Marek Vasut5ff05292020-01-24 18:39:16 +010081 unsigned char enetaddr[6];
Marek Vasut2ab7a2a2020-03-31 19:51:29 +020082 struct udevice *dev;
83 int off, ret;
Marek Vasut5ff05292020-01-24 18:39:16 +010084
85 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
86 if (ret) /* ethaddr is already set */
87 return 0;
88
Marek Vasut2ab7a2a2020-03-31 19:51:29 +020089 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
90 if (off < 0) {
91 printf("%s: No eeprom0 path offset\n", __func__);
92 return off;
Marek Vasut5ff05292020-01-24 18:39:16 +010093 }
94
Marek Vasut2ab7a2a2020-03-31 19:51:29 +020095 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
Marek Vasut5ff05292020-01-24 18:39:16 +010096 if (ret) {
97 printf("Cannot find EEPROM!\n");
98 return ret;
99 }
100
101 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
102 if (ret) {
103 printf("Error reading configuration EEPROM!\n");
104 return ret;
105 }
106
107 if (is_valid_ethaddr(enetaddr))
108 eth_env_set_enetaddr("ethaddr", enetaddr);
109
110 return 0;
111}
112
113int checkboard(void)
114{
115 char *mode;
116 const char *fdt_compat;
117 int fdt_compat_len;
118
Patrick Delaunay472407a2020-03-18 09:22:49 +0100119 if (IS_ENABLED(CONFIG_TFABOOT))
Marek Vasut5ff05292020-01-24 18:39:16 +0100120 mode = "trusted";
121 else
122 mode = "basic";
123
124 printf("Board: stm32mp1 in %s mode", mode);
125 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
126 &fdt_compat_len);
127 if (fdt_compat && fdt_compat_len)
128 printf(" (%s)", fdt_compat);
129 puts("\n");
130
131 return 0;
132}
133
Marek Vasut47b98ba2020-04-22 13:18:11 +0200134#ifdef CONFIG_BOARD_EARLY_INIT_F
135static u8 brdcode __section("data");
Marek Vasut39221b52020-04-22 13:18:14 +0200136static u8 ddr3code __section("data");
Marek Vasut47b98ba2020-04-22 13:18:11 +0200137static u8 somcode __section("data");
138
139static void board_get_coding_straps(void)
140{
141 struct gpio_desc gpio[4];
142 ofnode node;
143 int i, ret;
144
145 node = ofnode_path("/config");
146 if (!ofnode_valid(node)) {
147 printf("%s: no /config node?\n", __func__);
148 return;
149 }
150
151 brdcode = 0;
Marek Vasut39221b52020-04-22 13:18:14 +0200152 ddr3code = 0;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200153 somcode = 0;
154
155 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
156 gpio, ARRAY_SIZE(gpio),
157 GPIOD_IS_IN);
158 for (i = 0; i < ret; i++)
159 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
160
Marek Vasut39221b52020-04-22 13:18:14 +0200161 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
162 gpio, ARRAY_SIZE(gpio),
163 GPIOD_IS_IN);
164 for (i = 0; i < ret; i++)
165 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
166
Marek Vasut47b98ba2020-04-22 13:18:11 +0200167 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
168 gpio, ARRAY_SIZE(gpio),
169 GPIOD_IS_IN);
170 for (i = 0; i < ret; i++)
171 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
172
Marek Vasut39221b52020-04-22 13:18:14 +0200173 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
174 somcode, ddr3code, brdcode);
175}
176
177int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
178 const char *name)
179{
Marek Vasut272198e2020-04-29 15:08:38 +0200180 if (ddr3code == 1 &&
181 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
182 return 0;
183
Marek Vasut39221b52020-04-22 13:18:14 +0200184 if (ddr3code == 2 &&
Marek Vasut272198e2020-04-29 15:08:38 +0200185 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
Marek Vasut39221b52020-04-22 13:18:14 +0200186 return 0;
187
188 if (ddr3code == 3 &&
Marek Vasut272198e2020-04-29 15:08:38 +0200189 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
Marek Vasut39221b52020-04-22 13:18:14 +0200190 return 0;
191
192 return -EINVAL;
Marek Vasut47b98ba2020-04-22 13:18:11 +0200193}
194
195int board_early_init_f(void)
196{
197 board_get_coding_straps();
198
199 return 0;
200}
201
202#ifdef CONFIG_SPL_LOAD_FIT
203int board_fit_config_name_match(const char *name)
204{
205 char test[20];
206
207 snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
208
209 if (!strcmp(name, test))
210 return 0;
211
212 return -EINVAL;
213}
214#endif
215#endif
216
Marek Vasut5ff05292020-01-24 18:39:16 +0100217static void board_key_check(void)
218{
219#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
220 ofnode node;
221 struct gpio_desc gpio;
222 enum forced_boot_mode boot_mode = BOOT_NORMAL;
223
224 node = ofnode_path("/config");
225 if (!ofnode_valid(node)) {
226 debug("%s: no /config node?\n", __func__);
227 return;
228 }
229#ifdef CONFIG_FASTBOOT
230 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
231 &gpio, GPIOD_IS_IN)) {
232 debug("%s: could not find a /config/st,fastboot-gpios\n",
233 __func__);
234 } else {
235 if (dm_gpio_get_value(&gpio)) {
236 puts("Fastboot key pressed, ");
237 boot_mode = BOOT_FASTBOOT;
238 }
239
240 dm_gpio_free(NULL, &gpio);
241 }
242#endif
243#ifdef CONFIG_CMD_STM32PROG
244 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
245 &gpio, GPIOD_IS_IN)) {
246 debug("%s: could not find a /config/st,stm32prog-gpios\n",
247 __func__);
248 } else {
249 if (dm_gpio_get_value(&gpio)) {
250 puts("STM32Programmer key pressed, ");
251 boot_mode = BOOT_STM32PROG;
252 }
253 dm_gpio_free(NULL, &gpio);
254 }
255#endif
256
257 if (boot_mode != BOOT_NORMAL) {
258 puts("entering download mode...\n");
259 clrsetbits_le32(TAMP_BOOT_CONTEXT,
260 TAMP_BOOT_FORCED_MASK,
261 boot_mode);
262 }
263#endif
264}
265
266#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
267
268#include <usb/dwc2_udc.h>
269int g_dnl_board_usb_cable_connected(void)
270{
271 struct udevice *dwc2_udc_otg;
272 int ret;
273
274 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
275 DM_GET_DRIVER(dwc2_udc_otg),
276 &dwc2_udc_otg);
277 if (!ret)
278 debug("dwc2_udc_otg init failed\n");
279
280 return dwc2_udc_B_session_valid(dwc2_udc_otg);
281}
282
283#define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
284#define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
285
286int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
287{
288 if (!strcmp(name, "usb_dnl_dfu"))
289 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
290 else if (!strcmp(name, "usb_dnl_fastboot"))
291 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
292 &dev->idProduct);
293 else
294 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
295
296 return 0;
297}
298
299#endif /* CONFIG_USB_GADGET */
300
301#ifdef CONFIG_LED
302static int get_led(struct udevice **dev, char *led_string)
303{
304 char *led_name;
305 int ret;
306
307 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
308 if (!led_name) {
309 pr_debug("%s: could not find %s config string\n",
310 __func__, led_string);
311 return -ENOENT;
312 }
313 ret = led_get_by_label(led_name, dev);
314 if (ret) {
315 debug("%s: get=%d\n", __func__, ret);
316 return ret;
317 }
318
319 return 0;
320}
321
322static int setup_led(enum led_state_t cmd)
323{
324 struct udevice *dev;
325 int ret;
326
327 ret = get_led(&dev, "u-boot,boot-led");
328 if (ret)
329 return ret;
330
331 ret = led_set_state(dev, cmd);
332 return ret;
333}
334#endif
335
336static void __maybe_unused led_error_blink(u32 nb_blink)
337{
338#ifdef CONFIG_LED
339 int ret;
340 struct udevice *led;
341 u32 i;
342#endif
343
344 if (!nb_blink)
345 return;
346
347#ifdef CONFIG_LED
348 ret = get_led(&led, "u-boot,error-led");
349 if (!ret) {
350 /* make u-boot,error-led blinking */
351 /* if U32_MAX and 125ms interval, for 17.02 years */
352 for (i = 0; i < 2 * nb_blink; i++) {
353 led_set_state(led, LEDST_TOGGLE);
354 mdelay(125);
355 WATCHDOG_RESET();
356 }
357 }
358#endif
359
360 /* infinite: the boot process must be stopped */
361 if (nb_blink == U32_MAX)
362 hang();
363}
364
365static void sysconf_init(void)
366{
Patrick Delaunayf8fe21d2020-04-01 09:07:33 +0200367#ifndef CONFIG_TFABOOT
Marek Vasut5ff05292020-01-24 18:39:16 +0100368 u8 *syscfg;
369#ifdef CONFIG_DM_REGULATOR
370 struct udevice *pwr_dev;
371 struct udevice *pwr_reg;
372 struct udevice *dev;
373 int ret;
374 u32 otp = 0;
375#endif
376 u32 bootr;
377
378 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
379
380 /* interconnect update : select master using the port 1 */
381 /* LTDC = AXI_M9 */
382 /* GPU = AXI_M8 */
383 /* today information is hardcoded in U-Boot */
384 writel(BIT(9), syscfg + SYSCFG_ICNR);
385
386 /* disable Pull-Down for boot pin connected to VDD */
387 bootr = readl(syscfg + SYSCFG_BOOTR);
388 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
389 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
390 writel(bootr, syscfg + SYSCFG_BOOTR);
391
392#ifdef CONFIG_DM_REGULATOR
393 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
394 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
395 * The customer will have to disable this for low frequencies
396 * or if AFMUX is selected but the function not used, typically for
397 * TRACE. Otherwise, impact on power consumption.
398 *
399 * WARNING:
400 * enabling High Speed mode while VDD>2.7V
401 * with the OTP product_below_2v5 (OTP 18, BIT 13)
402 * erroneously set to 1 can damage the IC!
403 * => U-Boot set the register only if VDD < 2.7V (in DT)
404 * but this value need to be consistent with board design
405 */
406 ret = uclass_get_device_by_driver(UCLASS_PMIC,
407 DM_GET_DRIVER(stm32mp_pwr_pmic),
408 &pwr_dev);
409 if (!ret) {
410 ret = uclass_get_device_by_driver(UCLASS_MISC,
411 DM_GET_DRIVER(stm32mp_bsec),
412 &dev);
413 if (ret) {
414 pr_err("Can't find stm32mp_bsec driver\n");
415 return;
416 }
417
418 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
419 if (ret > 0)
420 otp = otp & BIT(13);
421
422 /* get VDD = vdd-supply */
423 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
424 &pwr_reg);
425
426 /* check if VDD is Low Voltage */
427 if (!ret) {
428 if (regulator_get_value(pwr_reg) < 2700000) {
429 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
430 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
431 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
432 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
433 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
434 syscfg + SYSCFG_IOCTRLSETR);
435
436 if (!otp)
437 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
438 } else {
439 if (otp)
440 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
441 }
442 } else {
443 debug("VDD unknown");
444 }
445 }
446#endif
447
448 /* activate automatic I/O compensation
449 * warning: need to ensure CSI enabled and ready in clock driver
450 */
451 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
452
453 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
454 ;
455 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
456#endif
457}
458
Marek Vasut0839ea92020-03-28 02:01:58 +0100459static void board_init_fmc2(void)
460{
461#define STM32_FMC2_BCR1 0x0
462#define STM32_FMC2_BTR1 0x4
463#define STM32_FMC2_BWTR1 0x104
464#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
465#define STM32_FMC2_BCRx_FMCEN BIT(31)
466#define STM32_FMC2_BCRx_WREN BIT(12)
467#define STM32_FMC2_BCRx_RSVD BIT(7)
468#define STM32_FMC2_BCRx_FACCEN BIT(6)
469#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
470#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
471#define STM32_FMC2_BCRx_MUXEN BIT(1)
472#define STM32_FMC2_BCRx_MBKEN BIT(0)
473#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
474#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
475#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
476#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
477#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
478#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
479
480#define RCC_MP_AHB6RSTCLRR 0x218
481#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
482#define RCC_MP_AHB6ENSETR 0x19c
483#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
484
485 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
486 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
487 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
488 STM32_FMC2_BCRx_MBKEN;
489 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
490 STM32_FMC2_BTRx_BUSTURN(2) |
491 STM32_FMC2_BTRx_DATAST(0x22) |
492 STM32_FMC2_BTRx_ADDHLD(2) |
493 STM32_FMC2_BTRx_ADDSET(2);
494
495 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
496 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
497 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
498
499 /* KS8851-16MLL -- Muxed mode */
500 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
501 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
502 /* AS7C34098 SRAM on X11 -- Muxed mode */
503 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
504 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
505
506 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
507}
508
Marek Vasut5ff05292020-01-24 18:39:16 +0100509/* board dependent setup after realloc */
510int board_init(void)
511{
512 struct udevice *dev;
513
514 /* address of boot parameters */
515 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
516
517 /* probe all PINCTRL for hog */
518 for (uclass_first_device(UCLASS_PINCTRL, &dev);
519 dev;
520 uclass_next_device(&dev)) {
521 pr_debug("probe pincontrol = %s\n", dev->name);
522 }
523
524 board_key_check();
525
526#ifdef CONFIG_DM_REGULATOR
527 regulators_enable_boot_on(_DEBUG);
528#endif
529
530 sysconf_init();
531
Marek Vasut0839ea92020-03-28 02:01:58 +0100532 board_init_fmc2();
533
Patrick Delaunay78f68f22020-04-10 19:14:01 +0200534 if (CONFIG_IS_ENABLED(LED))
Marek Vasut5ff05292020-01-24 18:39:16 +0100535 led_default_state();
536
537 return 0;
538}
539
540int board_late_init(void)
541{
542 char *boot_device;
543#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
544 const void *fdt_compat;
545 int fdt_compat_len;
546
547 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
548 &fdt_compat_len);
549 if (fdt_compat && fdt_compat_len) {
550 if (strncmp(fdt_compat, "st,", 3) != 0)
551 env_set("board_name", fdt_compat);
552 else
553 env_set("board_name", fdt_compat + 3);
554 }
555#endif
556
557 /* Check the boot-source to disable bootdelay */
558 boot_device = env_get("boot_device");
559 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
560 env_set("bootdelay", "0");
561
Marek Vasut47b98ba2020-04-22 13:18:11 +0200562#ifdef CONFIG_BOARD_EARLY_INIT_F
563 env_set_ulong("dh_som_rev", somcode);
564 env_set_ulong("dh_board_rev", brdcode);
Marek Vasut39221b52020-04-22 13:18:14 +0200565 env_set_ulong("dh_ddr3_code", ddr3code);
Marek Vasut47b98ba2020-04-22 13:18:11 +0200566#endif
567
Marek Vasut5ff05292020-01-24 18:39:16 +0100568 return 0;
569}
570
571void board_quiesce_devices(void)
572{
573#ifdef CONFIG_LED
574 setup_led(LEDST_OFF);
575#endif
576}
577
578/* eth init function : weak called in eqos driver */
579int board_interface_eth_init(struct udevice *dev,
580 phy_interface_t interface_type)
581{
582 u8 *syscfg;
583 u32 value;
584 bool eth_clk_sel_reg = false;
585 bool eth_ref_clk_sel_reg = false;
586
587 /* Gigabit Ethernet 125MHz clock selection. */
588 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
589
590 /* Ethernet 50Mhz RMII clock selection */
591 eth_ref_clk_sel_reg =
592 dev_read_bool(dev, "st,eth_ref_clk_sel");
593
594 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
595
596 if (!syscfg)
597 return -ENODEV;
598
599 switch (interface_type) {
600 case PHY_INTERFACE_MODE_MII:
601 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
602 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
603 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
604 break;
605 case PHY_INTERFACE_MODE_GMII:
606 if (eth_clk_sel_reg)
607 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
608 SYSCFG_PMCSETR_ETH_CLK_SEL;
609 else
610 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
611 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
612 break;
613 case PHY_INTERFACE_MODE_RMII:
614 if (eth_ref_clk_sel_reg)
615 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
616 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
617 else
618 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
619 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
620 break;
621 case PHY_INTERFACE_MODE_RGMII:
622 case PHY_INTERFACE_MODE_RGMII_ID:
623 case PHY_INTERFACE_MODE_RGMII_RXID:
624 case PHY_INTERFACE_MODE_RGMII_TXID:
625 if (eth_clk_sel_reg)
626 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
627 SYSCFG_PMCSETR_ETH_CLK_SEL;
628 else
629 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
630 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
631 break;
632 default:
633 debug("%s: Do not manage %d interface\n",
634 __func__, interface_type);
635 /* Do not manage others interfaces */
636 return -EINVAL;
637 }
638
639 /* clear and set ETH configuration bits */
640 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
641 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
642 syscfg + SYSCFG_PMCCLRR);
643 writel(value, syscfg + SYSCFG_PMCSETR);
644
645 return 0;
646}
647
648enum env_location env_get_location(enum env_operation op, int prio)
649{
650 if (prio)
651 return ENVL_UNKNOWN;
652
653#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
654 return ENVL_SPI_FLASH;
655#else
656 return ENVL_NOWHERE;
657#endif
658}
659
Marek Vasut5ff05292020-01-24 18:39:16 +0100660#if defined(CONFIG_OF_BOARD_SETUP)
661int ft_board_setup(void *blob, bd_t *bd)
662{
663 return 0;
664}
665#endif
666
Marek Vasut5ff05292020-01-24 18:39:16 +0100667static void board_copro_image_process(ulong fw_image, size_t fw_size)
668{
669 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
670
671 if (!rproc_is_initialized())
672 if (rproc_init()) {
673 printf("Remote Processor %d initialization failed\n",
674 id);
675 return;
676 }
677
678 ret = rproc_load(id, fw_image, fw_size);
679 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
680 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
681
682 if (!ret) {
683 rproc_start(id);
684 env_set("copro_state", "booted");
685 }
686}
687
688U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);