| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 2 | /* |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 3 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 4 | */ |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 5 | #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ |
| 6 | #define __CONFIG_SOCFPGA_CYCLONE5_H__ | ||||
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 7 | |
| Dinh Nguyen | eca8b5c | 2015-11-23 17:27:17 -0600 | [diff] [blame] | 8 | #include <asm/arch/base_addr_ac5.h> |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 9 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 10 | /* Memory configurations */ |
| Marek Vasut | d4a4db1 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 11 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 12 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 13 | /* The rest of the configuration is shared */ |
| 14 | #include <configs/socfpga_common.h> | ||||
| Chin Liang See | 561c9d4 | 2014-06-10 01:11:04 -0500 | [diff] [blame] | 15 | |
| Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 16 | #endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ |