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git01.mediatek.com / filogic / uboot / b02712ffb858d429fed206af50e9411fc9eac9bb / . / include / configs / sama5d27_wlsom1_ek.h
blob: e611e7b51047bfe7006573452db26d1da0e80123 [file] [log] [blame]
Nicolas Ferre8ba10c72019-08-08 07:48:26 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Configuration file for the SAMA5D27 WLSOM1 EK Board.
4 *
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#include "at91-sama5_common.h"
14
15#undef CONFIG_SYS_AT91_MAIN_CLOCK
16#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */
17
18/* SDRAM */
19#define CONFIG_SYS_SDRAM_BASE 0x20000000
20#define CONFIG_SYS_SDRAM_SIZE 0x10000000
21
Eugen Hristev1d152122019-08-08 07:48:35 +0000[diff] [blame]22#ifdef CONFIG_SPL_BUILD
23#define CONFIG_SYS_INIT_SP_ADDR 0x218000
24#else
Nicolas Ferre8ba10c72019-08-08 07:48:26 +0000[diff] [blame]25#define CONFIG_SYS_INIT_SP_ADDR \
26 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Eugen Hristev1d152122019-08-08 07:48:35 +0000[diff] [blame]27#endif
Nicolas Ferre8ba10c72019-08-08 07:48:26 +0000[diff] [blame]28
Eugen Hristev1d152122019-08-08 07:48:35 +0000[diff] [blame]29/* SPL */
Eugen Hristev1d152122019-08-08 07:48:35 +0000[diff] [blame]30#define CONFIG_SPL_MAX_SIZE 0x10000
31#define CONFIG_SPL_BSS_START_ADDR 0x20000000
32#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
33#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
34#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
35
36#define CONFIG_SYS_MONITOR_LEN (512 << 10)
Nicolas Ferre8ba10c72019-08-08 07:48:26 +0000[diff] [blame]37
38#ifdef CONFIG_SD_BOOT
Eugen Hristev1d152122019-08-08 07:48:35 +0000[diff] [blame]39#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Nicolas Ferre8ba10c72019-08-08 07:48:26 +0000[diff] [blame]40#endif
41
Nicolas Ferre8ba10c72019-08-08 07:48:26 +0000[diff] [blame]42#endif