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Stefan Roese115802d2018-08-16 15:27:31 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H
7#define __CONFIG_GARDENA_SMART_GATEWAY_H
8
9/* CPU */
Stefan Roesedcb9a992019-01-31 07:24:43 +010010#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000
Stefan Roese115802d2018-08-16 15:27:31 +020011
12/* RAM */
13#define CONFIG_SYS_SDRAM_BASE 0x80000000
14
Stefan Roese115802d2018-08-16 15:27:31 +020015#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
16
developer9720bc32020-04-21 09:28:48 +020017/* SPL */
Stefan Roese115802d2018-08-16 15:27:31 +020018
developer9720bc32020-04-21 09:28:48 +020019#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
20#define CONFIG_SPL_BSS_START_ADDR 0x80010000
21#define CONFIG_SPL_BSS_MAX_SIZE 0x10000
22#define CONFIG_SPL_MAX_SIZE 0x10000
23#define CONFIG_SPL_PAD_TO 0
24
25/* Dummy value */
26#define CONFIG_SYS_UBOOT_BASE 0
27
28/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -060029#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
developer9720bc32020-04-21 09:28:48 +020030#define CONFIG_SYS_NS16550_MEM32
31#define CONFIG_SYS_NS16550_CLK 40000000
32#define CONFIG_SYS_NS16550_REG_SIZE -4
33#define CONFIG_SYS_NS16550_COM1 0xb0000c00
developer9720bc32020-04-21 09:28:48 +020034#endif
35
Stefan Roese115802d2018-08-16 15:27:31 +020036/* UART */
37#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
developere1693432019-09-25 17:45:42 +080038 230400, 460800, 921600 }
Stefan Roese115802d2018-08-16 15:27:31 +020039
40/* RAM */
Stefan Roese115802d2018-08-16 15:27:31 +020041
42/* Memory usage */
43#define CONFIG_SYS_MAXARGS 64
Stefan Roese115802d2018-08-16 15:27:31 +020044#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
45#define CONFIG_SYS_CBSIZE 512
46
Stefan Roese115802d2018-08-16 15:27:31 +020047/* Environment settings */
Stefan Roese115802d2018-08-16 15:27:31 +020048
Stefan Roese115802d2018-08-16 15:27:31 +020049#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */