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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
2 * (C) Copyright 2000, 2001
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * FPGA support
27 */
28#include <common.h>
29#include <command.h>
wdenk57b2d802003-06-27 21:31:46 +000030#include <fpga.h>
wdenk525d7b62005-01-22 18:13:04 +000031#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000032
wdenk4a9cbbe2002-08-27 09:48:53 +000033/* Local functions */
Michal Simeka888af72013-04-26 13:10:07 +020034static int fpga_get_op(char *opstr);
wdenk4a9cbbe2002-08-27 09:48:53 +000035
36/* Local defines */
37#define FPGA_NONE -1
38#define FPGA_INFO 0
39#define FPGA_LOAD 1
wdenk310b4fc2005-01-09 18:12:51 +000040#define FPGA_LOADB 2
wdenk4a9cbbe2002-08-27 09:48:53 +000041#define FPGA_DUMP 3
Stefan Roese5f1cf2d2006-08-15 14:15:51 +020042#define FPGA_LOADMK 4
wdenk4a9cbbe2002-08-27 09:48:53 +000043
44/* ------------------------------------------------------------------------- */
45/* command form:
46 * fpga <op> <device number> <data addr> <datasize>
47 * where op is 'load', 'dump', or 'info'
48 * If there is no device number field, the fpga environment variable is used.
49 * If there is no data addr field, the fpgadata environment variable is used.
50 * The info command requires no data address field.
51 */
Michal Simeka888af72013-04-26 13:10:07 +020052int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000053{
wdenk1ebf41e2004-01-02 14:00:00 +000054 int op, dev = FPGA_INVALID_DEVICE;
55 size_t data_size = 0;
56 void *fpga_data = NULL;
Michal Simeka888af72013-04-26 13:10:07 +020057 char *devstr = getenv("fpga");
58 char *datastr = getenv("fpgadata");
wdenk1ebf41e2004-01-02 14:00:00 +000059 int rc = FPGA_FAIL;
Stefano Babic67d7f562010-10-19 09:22:52 +020060 int wrong_parms = 0;
Michal Simeka888af72013-04-26 13:10:07 +020061#if defined(CONFIG_FIT)
Marian Balakowiczd79162d2008-03-12 10:33:01 +010062 const char *fit_uname = NULL;
63 ulong fit_addr;
64#endif
wdenk4a9cbbe2002-08-27 09:48:53 +000065
wdenk1ebf41e2004-01-02 14:00:00 +000066 if (devstr)
Michal Simeka888af72013-04-26 13:10:07 +020067 dev = (int) simple_strtoul(devstr, NULL, 16);
wdenk1ebf41e2004-01-02 14:00:00 +000068 if (datastr)
Michal Simeka888af72013-04-26 13:10:07 +020069 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
wdenk4a9cbbe2002-08-27 09:48:53 +000070
wdenk1ebf41e2004-01-02 14:00:00 +000071 switch (argc) {
72 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simeka888af72013-04-26 13:10:07 +020073 data_size = simple_strtoul(argv[4], NULL, 16);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010074
wdenk1ebf41e2004-01-02 14:00:00 +000075 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczd79162d2008-03-12 10:33:01 +010076#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +020077 if (fit_parse_subimage(argv[3], (ulong)fpga_data,
78 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +010079 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +020080 debug("* fpga: subimage '%s' from FIT image ",
81 fit_uname);
82 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010083 } else
84#endif
85 {
Michal Simeka888af72013-04-26 13:10:07 +020086 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000087 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simeka888af72013-04-26 13:10:07 +020088 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010089 }
Michal Simeka888af72013-04-26 13:10:07 +020090 debug("%s: fpga_data = 0x%x\n", __func__, (uint)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +010091
wdenk1ebf41e2004-01-02 14:00:00 +000092 case 3: /* fpga <op> <dev | data addr> */
Michal Simeka888af72013-04-26 13:10:07 +020093 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babicb69b9a52011-12-28 06:47:01 +000094 debug("%s: device = %d\n", __func__, dev);
wdenk1ebf41e2004-01-02 14:00:00 +000095 /* FIXME - this is a really weak test */
Michal Simeka888af72013-04-26 13:10:07 +020096 if ((argc == 3) && (dev > fpga_count())) {
97 /* must be buffer ptr */
Stefano Babicb69b9a52011-12-28 06:47:01 +000098 debug("%s: Assuming buffer pointer in arg 3\n",
Michal Simeka888af72013-04-26 13:10:07 +020099 __func__);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100100
101#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200102 if (fit_parse_subimage(argv[2], (ulong)fpga_data,
103 &fit_addr, &fit_uname)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100104 fpga_data = (void *)fit_addr;
Michal Simeka888af72013-04-26 13:10:07 +0200105 debug("* fpga: subimage '%s' from FIT image ",
106 fit_uname);
107 debug("at 0x%08lx\n", fit_addr);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100108 } else
109#endif
110 {
Michal Simeka888af72013-04-26 13:10:07 +0200111 fpga_data = (void *)dev;
112 debug("* fpga: cmdline image addr = 0x%08lx\n",
113 (ulong)fpga_data);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100114 }
115
Stefano Babicb69b9a52011-12-28 06:47:01 +0000116 debug("%s: fpga_data = 0x%x\n",
Michal Simeka888af72013-04-26 13:10:07 +0200117 __func__, (uint)fpga_data);
wdenk1ebf41e2004-01-02 14:00:00 +0000118 dev = FPGA_INVALID_DEVICE; /* reset device num */
119 }
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100120
wdenk1ebf41e2004-01-02 14:00:00 +0000121 case 2: /* fpga <op> */
Michal Simeka888af72013-04-26 13:10:07 +0200122 op = (int)fpga_get_op(argv[1]);
wdenk1ebf41e2004-01-02 14:00:00 +0000123 break;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100124
wdenk1ebf41e2004-01-02 14:00:00 +0000125 default:
Michal Simeka888af72013-04-26 13:10:07 +0200126 debug("%s: Too many or too few args (%d)\n", __func__, argc);
wdenk1ebf41e2004-01-02 14:00:00 +0000127 op = FPGA_NONE; /* force usage display */
128 break;
129 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000130
Stefano Babic67d7f562010-10-19 09:22:52 +0200131 if (dev == FPGA_INVALID_DEVICE) {
132 puts("FPGA device not specified\n");
133 op = FPGA_NONE;
134 }
135
136 switch (op) {
137 case FPGA_NONE:
138 case FPGA_INFO:
139 break;
140 case FPGA_LOAD:
141 case FPGA_LOADB:
142 case FPGA_DUMP:
143 if (!fpga_data || !data_size)
144 wrong_parms = 1;
145 break;
146 case FPGA_LOADMK:
147 if (!fpga_data)
148 wrong_parms = 1;
149 break;
150 }
151
152 if (wrong_parms) {
153 puts("Wrong parameters for FPGA request\n");
154 op = FPGA_NONE;
155 }
156
wdenk1ebf41e2004-01-02 14:00:00 +0000157 switch (op) {
158 case FPGA_NONE:
Simon Glassa06dfc72011-12-10 08:44:01 +0000159 return CMD_RET_USAGE;
wdenk4a9cbbe2002-08-27 09:48:53 +0000160
wdenk1ebf41e2004-01-02 14:00:00 +0000161 case FPGA_INFO:
Michal Simeka888af72013-04-26 13:10:07 +0200162 rc = fpga_info(dev);
wdenk1ebf41e2004-01-02 14:00:00 +0000163 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000164
wdenk1ebf41e2004-01-02 14:00:00 +0000165 case FPGA_LOAD:
Michal Simeka888af72013-04-26 13:10:07 +0200166 rc = fpga_load(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000167 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000168
wdenk310b4fc2005-01-09 18:12:51 +0000169 case FPGA_LOADB:
170 rc = fpga_loadbitstream(dev, fpga_data, data_size);
171 break;
172
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200173 case FPGA_LOADMK:
Michal Simeka888af72013-04-26 13:10:07 +0200174 switch (genimg_get_format(fpga_data)) {
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100175 case IMAGE_FORMAT_LEGACY:
176 {
Michal Simeka888af72013-04-26 13:10:07 +0200177 image_header_t *hdr =
178 (image_header_t *)fpga_data;
179 ulong data;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200180
Michal Simeka888af72013-04-26 13:10:07 +0200181 data = (ulong)image_get_data(hdr);
182 data_size = image_get_data_size(hdr);
183 rc = fpga_load(dev, (void *)data, data_size);
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200184 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100185 break;
186#if defined(CONFIG_FIT)
187 case IMAGE_FORMAT_FIT:
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100188 {
189 const void *fit_hdr = (const void *)fpga_data;
190 int noffset;
Wolfgang Denk74f9b382011-07-30 13:33:49 +0000191 const void *fit_data;
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100192
193 if (fit_uname == NULL) {
Michal Simeka888af72013-04-26 13:10:07 +0200194 puts("No FIT subimage unit name\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100195 return 1;
196 }
197
Michal Simeka888af72013-04-26 13:10:07 +0200198 if (!fit_check_format(fit_hdr)) {
199 puts("Bad FIT image format\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100200 return 1;
201 }
202
203 /* get fpga component image node offset */
Michal Simeka888af72013-04-26 13:10:07 +0200204 noffset = fit_image_get_node(fit_hdr,
205 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100206 if (noffset < 0) {
Michal Simeka888af72013-04-26 13:10:07 +0200207 printf("Can't find '%s' FIT subimage\n",
208 fit_uname);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100209 return 1;
210 }
211
212 /* verify integrity */
Simon Glass7428ad12013-05-07 06:11:57 +0000213 if (!fit_image_verify(fit_hdr, noffset)) {
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100214 puts ("Bad Data Hash\n");
215 return 1;
216 }
217
218 /* get fpga subimage data address and length */
Michal Simeka888af72013-04-26 13:10:07 +0200219 if (fit_image_get_data(fit_hdr, noffset,
220 &fit_data, &data_size)) {
221 puts("Fpga subimage data not found\n");
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100222 return 1;
223 }
224
Michal Simeka888af72013-04-26 13:10:07 +0200225 rc = fpga_load(dev, fit_data, data_size);
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100226 }
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100227 break;
228#endif
229 default:
Michal Simeka888af72013-04-26 13:10:07 +0200230 puts("** Unknown image type\n");
Marian Balakowiczdbdd16a2008-02-04 08:28:09 +0100231 rc = FPGA_FAIL;
232 break;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200233 }
234 break;
235
wdenk1ebf41e2004-01-02 14:00:00 +0000236 case FPGA_DUMP:
Michal Simeka888af72013-04-26 13:10:07 +0200237 rc = fpga_dump(dev, fpga_data, data_size);
wdenk1ebf41e2004-01-02 14:00:00 +0000238 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000239
wdenk1ebf41e2004-01-02 14:00:00 +0000240 default:
Michal Simeka888af72013-04-26 13:10:07 +0200241 printf("Unknown operation\n");
Simon Glassa06dfc72011-12-10 08:44:01 +0000242 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000243 }
Michal Simeka888af72013-04-26 13:10:07 +0200244 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000245}
246
wdenk4a9cbbe2002-08-27 09:48:53 +0000247/*
248 * Map op to supported operations. We don't use a table since we
249 * would just have to relocate it from flash anyway.
250 */
Michal Simeka888af72013-04-26 13:10:07 +0200251static int fpga_get_op(char *opstr)
wdenk4a9cbbe2002-08-27 09:48:53 +0000252{
253 int op = FPGA_NONE;
254
Michal Simeka888af72013-04-26 13:10:07 +0200255 if (!strcmp("info", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000256 op = FPGA_INFO;
Michal Simeka888af72013-04-26 13:10:07 +0200257 else if (!strcmp("loadb", opstr))
wdenk310b4fc2005-01-09 18:12:51 +0000258 op = FPGA_LOADB;
Michal Simeka888af72013-04-26 13:10:07 +0200259 else if (!strcmp("load", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000260 op = FPGA_LOAD;
Michal Simeka888af72013-04-26 13:10:07 +0200261 else if (!strcmp("loadmk", opstr))
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200262 op = FPGA_LOADMK;
Michal Simeka888af72013-04-26 13:10:07 +0200263 else if (!strcmp("dump", opstr))
wdenk4a9cbbe2002-08-27 09:48:53 +0000264 op = FPGA_DUMP;
wdenk4a9cbbe2002-08-27 09:48:53 +0000265
Michal Simeka888af72013-04-26 13:10:07 +0200266 if (op == FPGA_NONE)
267 printf("Unknown fpga operation \"%s\"\n", opstr);
268
wdenk4a9cbbe2002-08-27 09:48:53 +0000269 return op;
270}
271
Michal Simeka888af72013-04-26 13:10:07 +0200272U_BOOT_CMD(fpga, 6, 1, do_fpga,
273 "loadable FPGA image support",
274 "[operation type] [device number] [image address] [image size]\n"
275 "fpga operations:\n"
276 " dump\t[dev]\t\t\tLoad device to memory buffer\n"
277 " info\t[dev]\t\t\tlist known device information\n"
278 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
279 " loadb\t[dev] [address] [size]\t"
280 "Load device from bitstream buffer (Xilinx only)\n"
281 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100282#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200283 "\n"
284 "\tFor loadmk operating on FIT format uImage address must include\n"
285 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100286#endif
287);