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git01.mediatek.com / filogic / uboot / b00867b3c72629172aa790ef221177427f74836f / . / board / RRvision / video_ad7179.h
blob: 1fc1ef440763148af7945111103a42e41383b7d9 [file] [log] [blame]
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]1/*
2 * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
wdenkdccbda02003-07-14 22:13:32 +0000[diff] [blame]5 */
6
7#define VIDEO_ENCODER_NAME "Analog Devices AD7179"
8
9#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
10#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
11
12#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
13#undef VIDEO_MODE_RGB
14#define VIDEO_MODE_BPP 16
15
16#ifdef VIDEO_MODE_PAL
17#define VIDEO_ACTIVE_COLS 720
18#define VIDEO_ACTIVE_ROWS 576
19#define VIDEO_VISIBLE_COLS 640
20#define VIDEO_VISIBLE_ROWS 480
21#else
22#error "NTSC mode is not supported"
23#endif
24
25static unsigned char video_encoder_data[] = {
26 0x05, /* Mode Register 0 */
27 0x11, /* Mode Register 1 */
28 0x20, /* Mode Register 2 */
29 0x0C, /* Mode Register 3 */
30 0x01, /* Mode Register 4 */
31 0x00, /* Reserved */
32 0x00, /* Reserved */
33 0x04, /* Timing Register 0 */
34 0x00, /* Timing Register 1 */
35 0xCB, /* Subcarrier Frequency Register 0 */
36 0x0A, /* Subcarrier Frequency Register 1 */
37 0x09, /* Subcarrier Frequency Register 2 */
38 0x2A, /* Subcarrier Frequency Register 3 */
39 0x00, /* Subcarrier Phase */
40 0x00, /* Closed Captioning Ext Reg 0 */
41 0x00, /* Closed Captioning Ext Reg 1 */
42 0x00, /* Closed Captioning Reg 0 */
43 0x00, /* Closed Captioning Reg 1 */
44 0x00, /* Pedestal Control Reg 0 */
45 0x00, /* Pedestal Control Reg 1 */
46 0x00, /* Pedestal Control Reg 2 */
47 0x00, /* Pedestal Control Reg 3 */
48 0x00, /* CGMS_WSS Reg 0 */
49 0x00, /* CGMS_WSS Reg 0 */
50 0x00, /* CGMS_WSS Reg 0 */
51 0x00 /* Teletext Req. Control Reg */
52} ;