blob: 3a136155dd92984bd2669c5bb9c9f6571c97af9c [file] [log] [blame]
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01001// SPDX-License-Identifier: GPL-2.0+
2
3#include <common.h>
4#include <asm/io.h>
5#include <memalign.h>
6#include <nand.h>
Simon Glassd66c5f72020-02-03 07:36:15 -07007#include <linux/err.h>
Philippe Reynes5aa6cfb2019-03-15 15:14:36 +01008#include <linux/errno.h>
9#include <linux/io.h>
10#include <linux/ioport.h>
11#include <dm.h>
12
13#include "brcmnand.h"
14
15struct bcm6838_nand_soc {
16 struct brcmnand_soc soc;
17 void __iomem *base;
18};
19
20#define BCM6838_NAND_INT 0x00
21#define BCM6838_NAND_STATUS_SHIFT 0
22#define BCM6838_NAND_STATUS_MASK (0xfff << BCM6838_NAND_STATUS_SHIFT)
23#define BCM6838_NAND_ENABLE_SHIFT 16
24#define BCM6838_NAND_ENABLE_MASK (0xffff << BCM6838_NAND_ENABLE_SHIFT)
25
26enum {
27 BCM6838_NP_READ = BIT(0),
28 BCM6838_BLOCK_ERASE = BIT(1),
29 BCM6838_COPY_BACK = BIT(2),
30 BCM6838_PAGE_PGM = BIT(3),
31 BCM6838_CTRL_READY = BIT(4),
32 BCM6838_DEV_RBPIN = BIT(5),
33 BCM6838_ECC_ERR_UNC = BIT(6),
34 BCM6838_ECC_ERR_CORR = BIT(7),
35};
36
37static bool bcm6838_nand_intc_ack(struct brcmnand_soc *soc)
38{
39 struct bcm6838_nand_soc *priv =
40 container_of(soc, struct bcm6838_nand_soc, soc);
41 void __iomem *mmio = priv->base + BCM6838_NAND_INT;
42 u32 val = brcmnand_readl(mmio);
43
44 if (val & (BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT)) {
45 /* Ack interrupt */
46 val &= ~BCM6838_NAND_STATUS_MASK;
47 val |= BCM6838_CTRL_READY << BCM6838_NAND_STATUS_SHIFT;
48 brcmnand_writel(val, mmio);
49 return true;
50 }
51
52 return false;
53}
54
55static void bcm6838_nand_intc_set(struct brcmnand_soc *soc, bool en)
56{
57 struct bcm6838_nand_soc *priv =
58 container_of(soc, struct bcm6838_nand_soc, soc);
59 void __iomem *mmio = priv->base + BCM6838_NAND_INT;
60 u32 val = brcmnand_readl(mmio);
61
62 /* Don't ack any interrupts */
63 val &= ~BCM6838_NAND_STATUS_MASK;
64
65 if (en)
66 val |= BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT;
67 else
68 val &= ~(BCM6838_CTRL_READY << BCM6838_NAND_ENABLE_SHIFT);
69
70 brcmnand_writel(val, mmio);
71}
72
73static int bcm6838_nand_probe(struct udevice *dev)
74{
75 struct udevice *pdev = dev;
76 struct bcm6838_nand_soc *priv = dev_get_priv(dev);
77 struct brcmnand_soc *soc;
78 struct resource res;
79
80 soc = &priv->soc;
81
82 dev_read_resource_byname(pdev, "nand-int-base", &res);
83 priv->base = ioremap(res.start, resource_size(&res));
84 if (IS_ERR(priv->base))
85 return PTR_ERR(priv->base);
86
87 soc->ctlrdy_ack = bcm6838_nand_intc_ack;
88 soc->ctlrdy_set_enabled = bcm6838_nand_intc_set;
89
90 /* Disable and ack all interrupts */
91 brcmnand_writel(0, priv->base + BCM6838_NAND_INT);
92 brcmnand_writel(BCM6838_NAND_STATUS_MASK,
93 priv->base + BCM6838_NAND_INT);
94
95 return brcmnand_probe(pdev, soc);
96}
97
98static const struct udevice_id bcm6838_nand_dt_ids[] = {
99 {
100 .compatible = "brcm,nand-bcm6838",
101 },
102 { /* sentinel */ }
103};
104
105U_BOOT_DRIVER(bcm6838_nand) = {
106 .name = "bcm6838-nand",
107 .id = UCLASS_MTD,
108 .of_match = bcm6838_nand_dt_ids,
109 .probe = bcm6838_nand_probe,
110 .priv_auto_alloc_size = sizeof(struct bcm6838_nand_soc),
111};
112
113void board_nand_init(void)
114{
115 struct udevice *dev;
116 int ret;
117
118 ret = uclass_get_device_by_driver(UCLASS_MTD,
119 DM_GET_DRIVER(bcm6838_nand), &dev);
120 if (ret && ret != -ENODEV)
121 pr_err("Failed to initialize %s. (error %d)\n", dev->name,
122 ret);
123}