| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Jorge Ramirez-Ortiz | f5b3842 | 2017-06-26 15:52:49 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2017 Linaro |
| 4 | * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> |
| Jorge Ramirez-Ortiz | f5b3842 | 2017-06-26 15:52:49 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __HI3798cv200_H__ |
| 8 | #define __HI3798cv200_H__ |
| 9 | |
| 10 | #define REG_BASE_PERI_CTRL 0xF8A20000 |
| 11 | #define REG_BASE_CRG 0xF8A22000 |
| 12 | |
| 13 | /* DEVICES */ |
| 14 | #define REG_BASE_MCI 0xF9830000 |
| 15 | #define REG_BASE_UART0 0xF8B00000 |
| 16 | |
| 17 | /* PERI control registers (4KB) */ |
| 18 | /* USB2 PHY01 configuration register */ |
| 19 | #define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) |
| 20 | |
| 21 | /* PERI CRG registers (4KB) */ |
| 22 | /* USB2 CTRL0 clock and soft reset */ |
| 23 | #define PERI_CRG46 (REG_BASE_CRG + 0xb8) |
| 24 | #define USB2_BUS_CKEN (1<<0) |
| 25 | #define USB2_OHCI48M_CKEN (1<<1) |
| 26 | #define USB2_OHCI12M_CKEN (1<<2) |
| 27 | #define USB2_OTG_UTMI_CKEN (1<<3) |
| 28 | #define USB2_HST_PHY_CKEN (1<<4) |
| 29 | #define USB2_UTMI0_CKEN (1<<5) |
| 30 | #define USB2_BUS_SRST_REQ (1<<12) |
| 31 | #define USB2_UTMI0_SRST_REQ (1<<13) |
| 32 | #define USB2_HST_PHY_SYST_REQ (1<<16) |
| 33 | #define USB2_OTG_PHY_SYST_REQ (1<<17) |
| 34 | #define USB2_CLK48_SEL (1<<20) |
| 35 | |
| 36 | /* USB2 PHY clock and soft reset */ |
| 37 | #define PERI_CRG47 (REG_BASE_CRG + 0xbc) |
| 38 | #define USB2_PHY01_REF_CKEN (1 << 0) |
| 39 | #define USB2_PHY2_REF_CKEN (1 << 2) |
| 40 | #define USB2_PHY01_SRST_REQ (1 << 4) |
| 41 | #define USB2_PHY2_SRST_REQ (1 << 6) |
| 42 | #define USB2_PHY01_SRST_TREQ0 (1 << 8) |
| 43 | #define USB2_PHY01_SRST_TREQ1 (1 << 9) |
| 44 | #define USB2_PHY2_SRST_TREQ (1 << 10) |
| 45 | #define USB2_PHY01_REFCLK_SEL (1 << 12) |
| 46 | #define USB2_PHY2_REFCLK_SEL (1 << 14) |
| 47 | |
| 48 | |
| 49 | #endif |