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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roesee463bf32015-01-19 11:33:42 +01002/*
Stefan Roese44e7ebd2016-01-07 14:09:09 +01003 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
Stefan Roesee463bf32015-01-19 11:33:42 +01004 */
5
Marek Behún90555af2022-02-17 13:54:42 +01006#include <cpu_func.h>
Stefan Roese83097cf2015-11-25 07:37:00 +01007#include <dm.h>
Stefan Roese83097cf2015-11-25 07:37:00 +01008#include <fdtdec.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Pali Rohárcf97b822021-07-23 11:14:29 +020010#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Stefan Roesee463bf32015-01-19 11:33:42 +010013#include <spl.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Stefan Roesee463bf32015-01-19 11:33:42 +010015#include <asm/io.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/soc.h>
18
Simon Glassb58bfe02021-08-08 12:20:09 -060019#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \
Simon Glass081a45a2021-08-08 12:20:17 -060020 defined(CONFIG_SPL_SATA)
Pali Rohárcf97b822021-07-23 11:14:29 +020021
22/*
23 * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must
24 * point to the offset of kwbimage main header which is always at offset zero
25 * (defined by BootROM). Therefore other values of CONFIG_SYS_SPI_U_BOOT_OFFS
26 * makes U-Boot non-bootable.
27 */
28#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
29#if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) && CONFIG_SYS_SPI_U_BOOT_OFFS != 0
30#error CONFIG_SYS_SPI_U_BOOT_OFFS must be set to 0
31#endif
32#endif
33
34/*
Pali Roháraa6244e2023-01-09 00:52:09 +010035 * When loading U-Boot via SPL from eMMC, the kwbimage main header is stored at
36 * sector 0 and either on HW boot partition or on data partition. Choice of HW
37 * partition depends on what is configured in eMMC EXT_CSC register.
38 * When loading U-Boot via SPL from SD card, the kwbimage main header is stored
39 * at sector 1.
40 * Therefore MBR/GPT partition booting, fixed sector number and fixed eMMC HW
41 * partition number are unsupported due to limitation of Marvell BootROM.
42 * Correct sector number must be determined as runtime in mvebu SPL code based
43 * on the detected boot source. Otherwise U-Boot SPL would not be able to load
44 * U-Boot proper.
45 * Runtime mvebu SPL sector calculation code expects:
46 * - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0
47 * - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0
Pali Rohárcf97b822021-07-23 11:14:29 +020048 */
Simon Glassb58bfe02021-08-08 12:20:09 -060049#ifdef CONFIG_SPL_MMC
Pali Roháraa6244e2023-01-09 00:52:09 +010050#ifdef CONFIG_SYS_MMCSD_FS_BOOT
51#error CONFIG_SYS_MMCSD_FS_BOOT is unsupported
52#endif
53#ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
54#error CONFIG_SYS_MMCSD_FS_BOOT_PARTITION is unsupported
55#endif
Pali Rohárcefdc032023-01-08 13:31:41 +010056#ifdef CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG
57#error CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG is unsupported
58#endif
59#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION
60#error CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION is unsupported
61#endif
Pali Rohárcf97b822021-07-23 11:14:29 +020062#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
63#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported
64#endif
Pali Roháraa6244e2023-01-09 00:52:09 +010065#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
66#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR must be enabled for SD/eMMC boot support
67#endif
68#if !defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) || \
69 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR != 0
Pali Rohárcf97b822021-07-23 11:14:29 +020070#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0
71#endif
Pali Roháraa6244e2023-01-09 00:52:09 +010072#if !defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) || \
Josua Mayer929b4b82023-10-25 10:22:53 +020073 (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 && \
74 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 4096)
75#error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to either 0 or 4096
Pali Rohárcf97b822021-07-23 11:14:29 +020076#endif
77#endif
78
79/*
80 * When loading U-Boot via SPL from SATA disk, the kwbimage main header is
81 * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be
82 * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper.
83 */
Simon Glass081a45a2021-08-08 12:20:17 -060084#ifdef CONFIG_SPL_SATA
Marek Behún3a7bbd82022-01-14 14:31:45 +010085#if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || \
86 !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1
Pali Rohárcf97b822021-07-23 11:14:29 +020087#error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1
88#endif
89#endif
90
91/* Boot Type - block ID */
92#define IBR_HDR_I2C_ID 0x4D
93#define IBR_HDR_SPI_ID 0x5A
94#define IBR_HDR_NAND_ID 0x8B
95#define IBR_HDR_SATA_ID 0x78
96#define IBR_HDR_PEX_ID 0x9C
97#define IBR_HDR_UART_ID 0x69
98#define IBR_HDR_SDIO_ID 0xAE
99
Pali Rohár0f7df222021-10-22 12:41:10 +0200100/* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */
Pali Rohárcf97b822021-07-23 11:14:29 +0200101struct kwbimage_main_hdr_v1 {
Marek Behún031d1722022-01-14 14:31:43 +0100102 u8 blockid; /* 0x0 */
103 u8 flags; /* 0x1 */
104 u16 nandpagesize; /* 0x2-0x3 */
105 u32 blocksize; /* 0x4-0x7 */
106 u8 version; /* 0x8 */
107 u8 headersz_msb; /* 0x9 */
108 u16 headersz_lsb; /* 0xA-0xB */
109 u32 srcaddr; /* 0xC-0xF */
110 u32 destaddr; /* 0x10-0x13 */
111 u32 execaddr; /* 0x14-0x17 */
112 u8 options; /* 0x18 */
113 u8 nandblocksize; /* 0x19 */
114 u8 nandbadblklocation; /* 0x1A */
115 u8 reserved4; /* 0x1B */
116 u16 reserved5; /* 0x1C-0x1D */
117 u8 ext; /* 0x1E */
118 u8 checksum; /* 0x1F */
Pali Rohárcf97b822021-07-23 11:14:29 +0200119} __packed;
120
Simon Glassb58bfe02021-08-08 12:20:09 -0600121#ifdef CONFIG_SPL_MMC
Andre Przywara3cb12ef2021-07-12 11:06:49 +0100122u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
Pali Rohárcf97b822021-07-23 11:14:29 +0200123{
Pali Roháraa6244e2023-01-09 00:52:09 +0100124 return IS_SD(mmc) ? MMCSD_MODE_RAW : MMCSD_MODE_EMMCBOOT;
125}
Marek Vasutf9a921e2023-10-16 18:16:12 +0200126unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
127 unsigned long raw_sect)
Pali Roháraa6244e2023-01-09 00:52:09 +0100128{
129 return IS_SD(mmc) ? 1 : 0;
Pali Rohárcf97b822021-07-23 11:14:29 +0200130}
131#endif
132
Pali Rohár82420562022-01-14 14:31:41 +0100133static u32 checksum32(void *start, u32 len)
134{
135 u32 csum = 0;
136 u32 *p = start;
137
138 while (len > 0) {
139 csum += *p++;
140 len -= sizeof(u32);
141 };
142
143 return csum;
144}
145
146int spl_check_board_image(struct spl_image_info *spl_image,
147 const struct spl_boot_device *bootdev)
148{
149 u32 csum = *(u32 *)(spl_image->load_addr + spl_image->size - 4);
150
151 if (checksum32((void *)spl_image->load_addr,
152 spl_image->size - 4) != csum) {
153 printf("ERROR: Invalid data checksum in kwbimage\n");
154 return -EINVAL;
155 }
156
157 return 0;
158}
159
Pali Rohárcf97b822021-07-23 11:14:29 +0200160int spl_parse_board_header(struct spl_image_info *spl_image,
Pali Rohárdda8f882022-01-14 14:31:38 +0100161 const struct spl_boot_device *bootdev,
Pali Rohárcf97b822021-07-23 11:14:29 +0200162 const void *image_header, size_t size)
163{
164 const struct kwbimage_main_hdr_v1 *mhdr = image_header;
165
166 if (size < sizeof(*mhdr)) {
167 /* This should be compile time assert */
168 printf("FATAL ERROR: Image header size is too small\n");
169 hang();
170 }
171
172 /*
173 * Very basic check for image validity. We cannot check mhdr->checksum
174 * as it is calculated also from variable length extended headers
175 * (including SPL content) which is not included in U-Boot image_header.
176 */
177 if (mhdr->version != 1 ||
Pali Rohára157e122022-01-14 14:31:39 +0100178 ((mhdr->headersz_msb << 16) | mhdr->headersz_lsb) < sizeof(*mhdr)) {
179 printf("ERROR: Invalid kwbimage v1\n");
180 return -EINVAL;
181 }
182
Marek Behún556eab62022-01-14 14:31:44 +0100183 if (IS_ENABLED(CONFIG_SPL_SPI_FLASH_SUPPORT) &&
184 bootdev->boot_device == BOOT_DEVICE_SPI &&
Pali Rohára157e122022-01-14 14:31:39 +0100185 mhdr->blockid != IBR_HDR_SPI_ID) {
186 printf("ERROR: Wrong blockid (0x%x) in SPI kwbimage\n",
187 mhdr->blockid);
188 return -EINVAL;
189 }
Pali Rohára157e122022-01-14 14:31:39 +0100190
Marek Behún556eab62022-01-14 14:31:44 +0100191 if (IS_ENABLED(CONFIG_SPL_SATA) &&
192 bootdev->boot_device == BOOT_DEVICE_SATA &&
Pali Rohára157e122022-01-14 14:31:39 +0100193 mhdr->blockid != IBR_HDR_SATA_ID) {
194 printf("ERROR: Wrong blockid (0x%x) in SATA kwbimage\n",
195 mhdr->blockid);
196 return -EINVAL;
197 }
Pali Rohára157e122022-01-14 14:31:39 +0100198
Marek Behún556eab62022-01-14 14:31:44 +0100199 if (IS_ENABLED(CONFIG_SPL_MMC) &&
Pali Rohár78097252023-01-08 13:27:07 +0100200 (bootdev->boot_device == BOOT_DEVICE_MMC1) &&
Pali Rohára157e122022-01-14 14:31:39 +0100201 mhdr->blockid != IBR_HDR_SDIO_ID) {
202 printf("ERROR: Wrong blockid (0x%x) in SDIO kwbimage\n",
203 mhdr->blockid);
Pali Rohárcf97b822021-07-23 11:14:29 +0200204 return -EINVAL;
205 }
206
207 spl_image->offset = mhdr->srcaddr;
208
Pali Rohárcf97b822021-07-23 11:14:29 +0200209 /*
210 * For SATA srcaddr is specified in number of sectors.
Pali Rohárb4c49822023-03-29 21:25:52 +0200211 * Retrieve block size of the first SCSI device (same
212 * code used by the spl_sata_load_image_raw() function)
213 * or fallback to default sector size of 512 bytes.
Pali Rohárcf97b822021-07-23 11:14:29 +0200214 */
Pali Rohárb4c49822023-03-29 21:25:52 +0200215 if (IS_ENABLED(CONFIG_SPL_SATA) && mhdr->blockid == IBR_HDR_SATA_ID) {
216 struct blk_desc *blk_dev = blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0);
217 unsigned long blksz = blk_dev ? blk_dev->blksz : 512;
218 spl_image->offset *= blksz;
219 }
Pali Rohárcf97b822021-07-23 11:14:29 +0200220
Pali Roháreb7e1fc2022-01-14 14:31:37 +0100221 if (spl_image->offset % 4 != 0) {
222 printf("ERROR: Wrong srcaddr (0x%08x) in kwbimage\n",
223 spl_image->offset);
224 return -EINVAL;
225 }
226
227 if (mhdr->blocksize <= 4 || mhdr->blocksize % 4 != 0) {
228 printf("ERROR: Wrong blocksize (0x%08x) in kwbimage\n",
229 mhdr->blocksize);
230 return -EINVAL;
231 }
232
Pali Rohárcf97b822021-07-23 11:14:29 +0200233 spl_image->size = mhdr->blocksize;
234 spl_image->entry_point = mhdr->execaddr;
235 spl_image->load_addr = mhdr->destaddr;
236 spl_image->os = IH_OS_U_BOOT;
237 spl_image->name = "U-Boot";
238
239 return 0;
240}
241
Stefan Roese44e7ebd2016-01-07 14:09:09 +0100242u32 spl_boot_device(void)
243{
Pali Rohárda1be862021-07-23 11:14:26 +0200244 u32 boot_device = get_boot_device();
245
Pali Rohárcf97b822021-07-23 11:14:29 +0200246 switch (boot_device) {
Pali Rohárda1be862021-07-23 11:14:26 +0200247 /*
248 * Return to the BootROM to continue the Marvell xmodem
249 * UART boot protocol. As initiated by the kwboot tool.
250 *
251 * This can only be done by the BootROM since the beginning
252 * of the image is already read and interpreted by the BootROM.
253 * SPL has no chance to receive this information. So we
254 * need to return to the BootROM to enable this xmodem
255 * UART download. Use SPL infrastructure to return to BootROM.
Pali Rohárda1be862021-07-23 11:14:26 +0200256 */
Pali Rohárda1be862021-07-23 11:14:26 +0200257 case BOOT_DEVICE_UART:
Pali Rohárda1be862021-07-23 11:14:26 +0200258 return BOOT_DEVICE_BOOTROM;
Pali Rohárcf97b822021-07-23 11:14:29 +0200259
260 /*
261 * If SPL is compiled with chosen boot_device support
262 * then use SPL driver for loading U-Boot proper.
263 */
Simon Glassb58bfe02021-08-08 12:20:09 -0600264#ifdef CONFIG_SPL_MMC
Pali Rohárcf97b822021-07-23 11:14:29 +0200265 case BOOT_DEVICE_MMC1:
266 return BOOT_DEVICE_MMC1;
267#endif
Simon Glass081a45a2021-08-08 12:20:17 -0600268#ifdef CONFIG_SPL_SATA
Pali Rohár90a88982021-10-29 14:09:48 +0200269 case BOOT_DEVICE_SATA:
270 return BOOT_DEVICE_SATA;
Pali Rohárcf97b822021-07-23 11:14:29 +0200271#endif
272#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
273 case BOOT_DEVICE_SPI:
274 return BOOT_DEVICE_SPI;
275#endif
276
277 /*
278 * If SPL is not compiled with chosen boot_device support
279 * then return to the BootROM. BootROM supports loading
280 * U-Boot proper from any valid boot_device present in SAR
281 * register.
282 */
Pali Rohárda1be862021-07-23 11:14:26 +0200283 default:
Pali Rohárcf97b822021-07-23 11:14:29 +0200284 return BOOT_DEVICE_BOOTROM;
Pali Rohárda1be862021-07-23 11:14:26 +0200285 }
Stefan Roese63962132015-07-20 11:20:36 +0200286}
287
Pali Rohárd0f064d2022-08-02 11:55:19 +0200288void board_boot_order(u32 *spl_boot_list)
289{
290 spl_boot_list[0] = spl_boot_device();
291 if (spl_boot_list[0] != BOOT_DEVICE_BOOTROM)
292 spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
293}
294
Marek Behúnee76b4a2021-08-16 15:19:37 +0200295#else
296
297u32 spl_boot_device(void)
298{
299 return BOOT_DEVICE_BOOTROM;
300}
301
302#endif
303
Pali Rohára3a38e52021-07-23 11:14:25 +0200304int board_return_to_bootrom(struct spl_image_info *spl_image,
305 struct spl_boot_device *bootdev)
306{
Tom Rinia276bc72022-05-24 09:57:18 -0400307 u32 *regs = *(u32 **)(CONFIG_SPL_STACK + 4);
Pali Rohára3a38e52021-07-23 11:14:25 +0200308
309 printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]);
310 return_to_bootrom();
311
312 /* NOTREACHED - return_to_bootrom() does not return */
313 hang();
314}
315
Stefan Roesee463bf32015-01-19 11:33:42 +0100316void board_init_f(ulong dummy)
317{
Stefan Roese83097cf2015-11-25 07:37:00 +0100318 int ret;
319
Stefan Roesed7f2c122015-04-17 18:13:06 +0200320 /*
321 * Pin muxing needs to be done before UART output, since
322 * on A38x the UART pins need some re-muxing for output
323 * to work.
324 */
325 board_early_init_f();
326
Stefan Roese85bddff2019-04-12 16:42:28 +0200327 /*
328 * Use special translation offset for SPL. This needs to be
329 * configured *before* spl_init() is called as this function
330 * calls dm_init() which calls the bind functions of the
331 * device drivers. Here the base address needs to be configured
332 * (translated) correctly.
333 */
334 gd->translation_offset = 0xd0000000 - 0xf1000000;
335
Stefan Roese83097cf2015-11-25 07:37:00 +0100336 ret = spl_init();
337 if (ret) {
Pali Rohár6e863512021-12-17 18:31:14 +0100338 printf("spl_init() failed: %d\n", ret);
Stefan Roese83097cf2015-11-25 07:37:00 +0100339 hang();
340 }
341
Stefan Roesee463bf32015-01-19 11:33:42 +0100342 preloader_console_init();
343
Stefan Roese479f9af2016-02-10 07:23:00 +0100344 /* Armada 375 does not support SerDes and DDR3 init yet */
345#if !defined(CONFIG_ARMADA_375)
Stefan Roesee463bf32015-01-19 11:33:42 +0100346 /* First init the serdes PHY's */
347 serdes_phy_config();
348
349 /* Setup DDR */
Pali Rohárc87978a2021-08-09 17:44:35 +0200350 ret = ddr3_init();
351 if (ret) {
Pali Rohár6e863512021-12-17 18:31:14 +0100352 printf("ddr3_init() failed: %d\n", ret);
Marek Behún90555af2022-02-17 13:54:42 +0100353 if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
354 get_boot_device() != BOOT_DEVICE_UART)
355 reset_cpu();
356 else
357 hang();
Pali Rohárc87978a2021-08-09 17:44:35 +0200358 }
Stefan Roese479f9af2016-02-10 07:23:00 +0100359#endif
Stefan Roesee463bf32015-01-19 11:33:42 +0100360
Baruch Siach056e1072019-07-10 18:23:04 +0300361 /* Initialize Auto Voltage Scaling */
362 mv_avs_init();
363
Chris Packham3667bec2020-02-26 19:53:50 +1300364 /* Update read timing control for PCIe */
365 mv_rtc_config();
Stefan Roesee463bf32015-01-19 11:33:42 +0100366}