Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 2 | /* |
Stefan Roese | 44e7ebd | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 3 | * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
Marek Behún | 90555af | 2022-02-17 13:54:42 +0100 | [diff] [blame] | 6 | #include <cpu_func.h> |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 7 | #include <dm.h> |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 8 | #include <fdtdec.h> |
Simon Glass | f11478f | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 9 | #include <hang.h> |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 10 | #include <image.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 11 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 12 | #include <log.h> |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 13 | #include <spl.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 14 | #include <asm/global_data.h> |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/cpu.h> |
| 17 | #include <asm/arch/soc.h> |
| 18 | |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 19 | #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \ |
Simon Glass | 081a45a | 2021-08-08 12:20:17 -0600 | [diff] [blame] | 20 | defined(CONFIG_SPL_SATA) |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 21 | |
| 22 | /* |
| 23 | * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must |
| 24 | * point to the offset of kwbimage main header which is always at offset zero |
| 25 | * (defined by BootROM). Therefore other values of CONFIG_SYS_SPI_U_BOOT_OFFS |
| 26 | * makes U-Boot non-bootable. |
| 27 | */ |
| 28 | #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT |
| 29 | #if defined(CONFIG_SYS_SPI_U_BOOT_OFFS) && CONFIG_SYS_SPI_U_BOOT_OFFS != 0 |
| 30 | #error CONFIG_SYS_SPI_U_BOOT_OFFS must be set to 0 |
| 31 | #endif |
| 32 | #endif |
| 33 | |
| 34 | /* |
Pali Rohár | aa6244e | 2023-01-09 00:52:09 +0100 | [diff] [blame] | 35 | * When loading U-Boot via SPL from eMMC, the kwbimage main header is stored at |
| 36 | * sector 0 and either on HW boot partition or on data partition. Choice of HW |
| 37 | * partition depends on what is configured in eMMC EXT_CSC register. |
| 38 | * When loading U-Boot via SPL from SD card, the kwbimage main header is stored |
| 39 | * at sector 1. |
| 40 | * Therefore MBR/GPT partition booting, fixed sector number and fixed eMMC HW |
| 41 | * partition number are unsupported due to limitation of Marvell BootROM. |
| 42 | * Correct sector number must be determined as runtime in mvebu SPL code based |
| 43 | * on the detected boot source. Otherwise U-Boot SPL would not be able to load |
| 44 | * U-Boot proper. |
| 45 | * Runtime mvebu SPL sector calculation code expects: |
| 46 | * - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0 |
| 47 | * - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0 |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 48 | */ |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 49 | #ifdef CONFIG_SPL_MMC |
Pali Rohár | aa6244e | 2023-01-09 00:52:09 +0100 | [diff] [blame] | 50 | #ifdef CONFIG_SYS_MMCSD_FS_BOOT |
| 51 | #error CONFIG_SYS_MMCSD_FS_BOOT is unsupported |
| 52 | #endif |
| 53 | #ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION |
| 54 | #error CONFIG_SYS_MMCSD_FS_BOOT_PARTITION is unsupported |
| 55 | #endif |
Pali Rohár | cefdc03 | 2023-01-08 13:31:41 +0100 | [diff] [blame] | 56 | #ifdef CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG |
| 57 | #error CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG is unsupported |
| 58 | #endif |
| 59 | #ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION |
| 60 | #error CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION is unsupported |
| 61 | #endif |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 62 | #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
| 63 | #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported |
| 64 | #endif |
Pali Rohár | aa6244e | 2023-01-09 00:52:09 +0100 | [diff] [blame] | 65 | #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR |
| 66 | #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR must be enabled for SD/eMMC boot support |
| 67 | #endif |
| 68 | #if !defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) || \ |
| 69 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR != 0 |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 70 | #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0 |
| 71 | #endif |
Pali Rohár | aa6244e | 2023-01-09 00:52:09 +0100 | [diff] [blame] | 72 | #if !defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) || \ |
Josua Mayer | 929b4b8 | 2023-10-25 10:22:53 +0200 | [diff] [blame] | 73 | (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 && \ |
| 74 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 4096) |
| 75 | #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to either 0 or 4096 |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 76 | #endif |
| 77 | #endif |
| 78 | |
| 79 | /* |
| 80 | * When loading U-Boot via SPL from SATA disk, the kwbimage main header is |
| 81 | * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be |
| 82 | * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper. |
| 83 | */ |
Simon Glass | 081a45a | 2021-08-08 12:20:17 -0600 | [diff] [blame] | 84 | #ifdef CONFIG_SPL_SATA |
Marek Behún | 3a7bbd8 | 2022-01-14 14:31:45 +0100 | [diff] [blame] | 85 | #if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || \ |
| 86 | !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1 |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 87 | #error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1 |
| 88 | #endif |
| 89 | #endif |
| 90 | |
| 91 | /* Boot Type - block ID */ |
| 92 | #define IBR_HDR_I2C_ID 0x4D |
| 93 | #define IBR_HDR_SPI_ID 0x5A |
| 94 | #define IBR_HDR_NAND_ID 0x8B |
| 95 | #define IBR_HDR_SATA_ID 0x78 |
| 96 | #define IBR_HDR_PEX_ID 0x9C |
| 97 | #define IBR_HDR_UART_ID 0x69 |
| 98 | #define IBR_HDR_SDIO_ID 0xAE |
| 99 | |
Pali Rohár | 0f7df22 | 2021-10-22 12:41:10 +0200 | [diff] [blame] | 100 | /* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */ |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 101 | struct kwbimage_main_hdr_v1 { |
Marek Behún | 031d172 | 2022-01-14 14:31:43 +0100 | [diff] [blame] | 102 | u8 blockid; /* 0x0 */ |
| 103 | u8 flags; /* 0x1 */ |
| 104 | u16 nandpagesize; /* 0x2-0x3 */ |
| 105 | u32 blocksize; /* 0x4-0x7 */ |
| 106 | u8 version; /* 0x8 */ |
| 107 | u8 headersz_msb; /* 0x9 */ |
| 108 | u16 headersz_lsb; /* 0xA-0xB */ |
| 109 | u32 srcaddr; /* 0xC-0xF */ |
| 110 | u32 destaddr; /* 0x10-0x13 */ |
| 111 | u32 execaddr; /* 0x14-0x17 */ |
| 112 | u8 options; /* 0x18 */ |
| 113 | u8 nandblocksize; /* 0x19 */ |
| 114 | u8 nandbadblklocation; /* 0x1A */ |
| 115 | u8 reserved4; /* 0x1B */ |
| 116 | u16 reserved5; /* 0x1C-0x1D */ |
| 117 | u8 ext; /* 0x1E */ |
| 118 | u8 checksum; /* 0x1F */ |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 119 | } __packed; |
| 120 | |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 121 | #ifdef CONFIG_SPL_MMC |
Andre Przywara | 3cb12ef | 2021-07-12 11:06:49 +0100 | [diff] [blame] | 122 | u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 123 | { |
Pali Rohár | aa6244e | 2023-01-09 00:52:09 +0100 | [diff] [blame] | 124 | return IS_SD(mmc) ? MMCSD_MODE_RAW : MMCSD_MODE_EMMCBOOT; |
| 125 | } |
Marek Vasut | f9a921e | 2023-10-16 18:16:12 +0200 | [diff] [blame] | 126 | unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc, |
| 127 | unsigned long raw_sect) |
Pali Rohár | aa6244e | 2023-01-09 00:52:09 +0100 | [diff] [blame] | 128 | { |
| 129 | return IS_SD(mmc) ? 1 : 0; |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 130 | } |
| 131 | #endif |
| 132 | |
Pali Rohár | 8242056 | 2022-01-14 14:31:41 +0100 | [diff] [blame] | 133 | static u32 checksum32(void *start, u32 len) |
| 134 | { |
| 135 | u32 csum = 0; |
| 136 | u32 *p = start; |
| 137 | |
| 138 | while (len > 0) { |
| 139 | csum += *p++; |
| 140 | len -= sizeof(u32); |
| 141 | }; |
| 142 | |
| 143 | return csum; |
| 144 | } |
| 145 | |
| 146 | int spl_check_board_image(struct spl_image_info *spl_image, |
| 147 | const struct spl_boot_device *bootdev) |
| 148 | { |
| 149 | u32 csum = *(u32 *)(spl_image->load_addr + spl_image->size - 4); |
| 150 | |
| 151 | if (checksum32((void *)spl_image->load_addr, |
| 152 | spl_image->size - 4) != csum) { |
| 153 | printf("ERROR: Invalid data checksum in kwbimage\n"); |
| 154 | return -EINVAL; |
| 155 | } |
| 156 | |
| 157 | return 0; |
| 158 | } |
| 159 | |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 160 | int spl_parse_board_header(struct spl_image_info *spl_image, |
Pali Rohár | dda8f88 | 2022-01-14 14:31:38 +0100 | [diff] [blame] | 161 | const struct spl_boot_device *bootdev, |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 162 | const void *image_header, size_t size) |
| 163 | { |
| 164 | const struct kwbimage_main_hdr_v1 *mhdr = image_header; |
| 165 | |
| 166 | if (size < sizeof(*mhdr)) { |
| 167 | /* This should be compile time assert */ |
| 168 | printf("FATAL ERROR: Image header size is too small\n"); |
| 169 | hang(); |
| 170 | } |
| 171 | |
| 172 | /* |
| 173 | * Very basic check for image validity. We cannot check mhdr->checksum |
| 174 | * as it is calculated also from variable length extended headers |
| 175 | * (including SPL content) which is not included in U-Boot image_header. |
| 176 | */ |
| 177 | if (mhdr->version != 1 || |
Pali Rohár | a157e12 | 2022-01-14 14:31:39 +0100 | [diff] [blame] | 178 | ((mhdr->headersz_msb << 16) | mhdr->headersz_lsb) < sizeof(*mhdr)) { |
| 179 | printf("ERROR: Invalid kwbimage v1\n"); |
| 180 | return -EINVAL; |
| 181 | } |
| 182 | |
Marek Behún | 556eab6 | 2022-01-14 14:31:44 +0100 | [diff] [blame] | 183 | if (IS_ENABLED(CONFIG_SPL_SPI_FLASH_SUPPORT) && |
| 184 | bootdev->boot_device == BOOT_DEVICE_SPI && |
Pali Rohár | a157e12 | 2022-01-14 14:31:39 +0100 | [diff] [blame] | 185 | mhdr->blockid != IBR_HDR_SPI_ID) { |
| 186 | printf("ERROR: Wrong blockid (0x%x) in SPI kwbimage\n", |
| 187 | mhdr->blockid); |
| 188 | return -EINVAL; |
| 189 | } |
Pali Rohár | a157e12 | 2022-01-14 14:31:39 +0100 | [diff] [blame] | 190 | |
Marek Behún | 556eab6 | 2022-01-14 14:31:44 +0100 | [diff] [blame] | 191 | if (IS_ENABLED(CONFIG_SPL_SATA) && |
| 192 | bootdev->boot_device == BOOT_DEVICE_SATA && |
Pali Rohár | a157e12 | 2022-01-14 14:31:39 +0100 | [diff] [blame] | 193 | mhdr->blockid != IBR_HDR_SATA_ID) { |
| 194 | printf("ERROR: Wrong blockid (0x%x) in SATA kwbimage\n", |
| 195 | mhdr->blockid); |
| 196 | return -EINVAL; |
| 197 | } |
Pali Rohár | a157e12 | 2022-01-14 14:31:39 +0100 | [diff] [blame] | 198 | |
Marek Behún | 556eab6 | 2022-01-14 14:31:44 +0100 | [diff] [blame] | 199 | if (IS_ENABLED(CONFIG_SPL_MMC) && |
Pali Rohár | 7809725 | 2023-01-08 13:27:07 +0100 | [diff] [blame] | 200 | (bootdev->boot_device == BOOT_DEVICE_MMC1) && |
Pali Rohár | a157e12 | 2022-01-14 14:31:39 +0100 | [diff] [blame] | 201 | mhdr->blockid != IBR_HDR_SDIO_ID) { |
| 202 | printf("ERROR: Wrong blockid (0x%x) in SDIO kwbimage\n", |
| 203 | mhdr->blockid); |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 204 | return -EINVAL; |
| 205 | } |
| 206 | |
| 207 | spl_image->offset = mhdr->srcaddr; |
| 208 | |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 209 | /* |
| 210 | * For SATA srcaddr is specified in number of sectors. |
Pali Rohár | b4c4982 | 2023-03-29 21:25:52 +0200 | [diff] [blame] | 211 | * Retrieve block size of the first SCSI device (same |
| 212 | * code used by the spl_sata_load_image_raw() function) |
| 213 | * or fallback to default sector size of 512 bytes. |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 214 | */ |
Pali Rohár | b4c4982 | 2023-03-29 21:25:52 +0200 | [diff] [blame] | 215 | if (IS_ENABLED(CONFIG_SPL_SATA) && mhdr->blockid == IBR_HDR_SATA_ID) { |
| 216 | struct blk_desc *blk_dev = blk_get_devnum_by_uclass_id(UCLASS_SCSI, 0); |
| 217 | unsigned long blksz = blk_dev ? blk_dev->blksz : 512; |
| 218 | spl_image->offset *= blksz; |
| 219 | } |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 220 | |
Pali Rohár | eb7e1fc | 2022-01-14 14:31:37 +0100 | [diff] [blame] | 221 | if (spl_image->offset % 4 != 0) { |
| 222 | printf("ERROR: Wrong srcaddr (0x%08x) in kwbimage\n", |
| 223 | spl_image->offset); |
| 224 | return -EINVAL; |
| 225 | } |
| 226 | |
| 227 | if (mhdr->blocksize <= 4 || mhdr->blocksize % 4 != 0) { |
| 228 | printf("ERROR: Wrong blocksize (0x%08x) in kwbimage\n", |
| 229 | mhdr->blocksize); |
| 230 | return -EINVAL; |
| 231 | } |
| 232 | |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 233 | spl_image->size = mhdr->blocksize; |
| 234 | spl_image->entry_point = mhdr->execaddr; |
| 235 | spl_image->load_addr = mhdr->destaddr; |
| 236 | spl_image->os = IH_OS_U_BOOT; |
| 237 | spl_image->name = "U-Boot"; |
| 238 | |
| 239 | return 0; |
| 240 | } |
| 241 | |
Stefan Roese | 44e7ebd | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 242 | u32 spl_boot_device(void) |
| 243 | { |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 244 | u32 boot_device = get_boot_device(); |
| 245 | |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 246 | switch (boot_device) { |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 247 | /* |
| 248 | * Return to the BootROM to continue the Marvell xmodem |
| 249 | * UART boot protocol. As initiated by the kwboot tool. |
| 250 | * |
| 251 | * This can only be done by the BootROM since the beginning |
| 252 | * of the image is already read and interpreted by the BootROM. |
| 253 | * SPL has no chance to receive this information. So we |
| 254 | * need to return to the BootROM to enable this xmodem |
| 255 | * UART download. Use SPL infrastructure to return to BootROM. |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 256 | */ |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 257 | case BOOT_DEVICE_UART: |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 258 | return BOOT_DEVICE_BOOTROM; |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 259 | |
| 260 | /* |
| 261 | * If SPL is compiled with chosen boot_device support |
| 262 | * then use SPL driver for loading U-Boot proper. |
| 263 | */ |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 264 | #ifdef CONFIG_SPL_MMC |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 265 | case BOOT_DEVICE_MMC1: |
| 266 | return BOOT_DEVICE_MMC1; |
| 267 | #endif |
Simon Glass | 081a45a | 2021-08-08 12:20:17 -0600 | [diff] [blame] | 268 | #ifdef CONFIG_SPL_SATA |
Pali Rohár | 90a8898 | 2021-10-29 14:09:48 +0200 | [diff] [blame] | 269 | case BOOT_DEVICE_SATA: |
| 270 | return BOOT_DEVICE_SATA; |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 271 | #endif |
| 272 | #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT |
| 273 | case BOOT_DEVICE_SPI: |
| 274 | return BOOT_DEVICE_SPI; |
| 275 | #endif |
| 276 | |
| 277 | /* |
| 278 | * If SPL is not compiled with chosen boot_device support |
| 279 | * then return to the BootROM. BootROM supports loading |
| 280 | * U-Boot proper from any valid boot_device present in SAR |
| 281 | * register. |
| 282 | */ |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 283 | default: |
Pali Rohár | cf97b82 | 2021-07-23 11:14:29 +0200 | [diff] [blame] | 284 | return BOOT_DEVICE_BOOTROM; |
Pali Rohár | da1be86 | 2021-07-23 11:14:26 +0200 | [diff] [blame] | 285 | } |
Stefan Roese | 6396213 | 2015-07-20 11:20:36 +0200 | [diff] [blame] | 286 | } |
| 287 | |
Pali Rohár | d0f064d | 2022-08-02 11:55:19 +0200 | [diff] [blame] | 288 | void board_boot_order(u32 *spl_boot_list) |
| 289 | { |
| 290 | spl_boot_list[0] = spl_boot_device(); |
| 291 | if (spl_boot_list[0] != BOOT_DEVICE_BOOTROM) |
| 292 | spl_boot_list[1] = BOOT_DEVICE_BOOTROM; |
| 293 | } |
| 294 | |
Marek Behún | ee76b4a | 2021-08-16 15:19:37 +0200 | [diff] [blame] | 295 | #else |
| 296 | |
| 297 | u32 spl_boot_device(void) |
| 298 | { |
| 299 | return BOOT_DEVICE_BOOTROM; |
| 300 | } |
| 301 | |
| 302 | #endif |
| 303 | |
Pali Rohár | a3a38e5 | 2021-07-23 11:14:25 +0200 | [diff] [blame] | 304 | int board_return_to_bootrom(struct spl_image_info *spl_image, |
| 305 | struct spl_boot_device *bootdev) |
| 306 | { |
Tom Rini | a276bc7 | 2022-05-24 09:57:18 -0400 | [diff] [blame] | 307 | u32 *regs = *(u32 **)(CONFIG_SPL_STACK + 4); |
Pali Rohár | a3a38e5 | 2021-07-23 11:14:25 +0200 | [diff] [blame] | 308 | |
| 309 | printf("Returning to BootROM (return address 0x%08x)...\n", regs[13]); |
| 310 | return_to_bootrom(); |
| 311 | |
| 312 | /* NOTREACHED - return_to_bootrom() does not return */ |
| 313 | hang(); |
| 314 | } |
| 315 | |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 316 | void board_init_f(ulong dummy) |
| 317 | { |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 318 | int ret; |
| 319 | |
Stefan Roese | d7f2c12 | 2015-04-17 18:13:06 +0200 | [diff] [blame] | 320 | /* |
| 321 | * Pin muxing needs to be done before UART output, since |
| 322 | * on A38x the UART pins need some re-muxing for output |
| 323 | * to work. |
| 324 | */ |
| 325 | board_early_init_f(); |
| 326 | |
Stefan Roese | 85bddff | 2019-04-12 16:42:28 +0200 | [diff] [blame] | 327 | /* |
| 328 | * Use special translation offset for SPL. This needs to be |
| 329 | * configured *before* spl_init() is called as this function |
| 330 | * calls dm_init() which calls the bind functions of the |
| 331 | * device drivers. Here the base address needs to be configured |
| 332 | * (translated) correctly. |
| 333 | */ |
| 334 | gd->translation_offset = 0xd0000000 - 0xf1000000; |
| 335 | |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 336 | ret = spl_init(); |
| 337 | if (ret) { |
Pali Rohár | 6e86351 | 2021-12-17 18:31:14 +0100 | [diff] [blame] | 338 | printf("spl_init() failed: %d\n", ret); |
Stefan Roese | 83097cf | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 339 | hang(); |
| 340 | } |
| 341 | |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 342 | preloader_console_init(); |
| 343 | |
Stefan Roese | 479f9af | 2016-02-10 07:23:00 +0100 | [diff] [blame] | 344 | /* Armada 375 does not support SerDes and DDR3 init yet */ |
| 345 | #if !defined(CONFIG_ARMADA_375) |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 346 | /* First init the serdes PHY's */ |
| 347 | serdes_phy_config(); |
| 348 | |
| 349 | /* Setup DDR */ |
Pali Rohár | c87978a | 2021-08-09 17:44:35 +0200 | [diff] [blame] | 350 | ret = ddr3_init(); |
| 351 | if (ret) { |
Pali Rohár | 6e86351 | 2021-12-17 18:31:14 +0100 | [diff] [blame] | 352 | printf("ddr3_init() failed: %d\n", ret); |
Marek Behún | 90555af | 2022-02-17 13:54:42 +0100 | [diff] [blame] | 353 | if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) && |
| 354 | get_boot_device() != BOOT_DEVICE_UART) |
| 355 | reset_cpu(); |
| 356 | else |
| 357 | hang(); |
Pali Rohár | c87978a | 2021-08-09 17:44:35 +0200 | [diff] [blame] | 358 | } |
Stefan Roese | 479f9af | 2016-02-10 07:23:00 +0100 | [diff] [blame] | 359 | #endif |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 360 | |
Baruch Siach | 056e107 | 2019-07-10 18:23:04 +0300 | [diff] [blame] | 361 | /* Initialize Auto Voltage Scaling */ |
| 362 | mv_avs_init(); |
| 363 | |
Chris Packham | 3667bec | 2020-02-26 19:53:50 +1300 | [diff] [blame] | 364 | /* Update read timing control for PCIe */ |
| 365 | mv_rtc_config(); |
Stefan Roese | e463bf3 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 366 | } |