Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / afa78aaf73763dd1fb77584ca5a9e87325bccb83 / . / arch / arm / include / asm / arch-vf610 / ddrmc-vf610.h
blob: 03e3cecb95a090c35a4311238d3d31b8857370cb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]2/*
3 * Copyright (C) 2015
4 * Toradex, Inc.
5 *
6 * Authors: Stefan Agner
7 * Sanchayan Maity
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]8 */
9
10#ifndef __ASM_ARCH_VF610_DDRMC_H
11#define __ASM_ARCH_VF610_DDRMC_H
12
Marcel Ziswiler3dc76a62019-03-25 17:24:52 +0100[diff] [blame]13#include <asm/arch/iomux-vf610.h>
14
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]15struct ddr3_jedec_timings {
16 u8 tinit;
17 u32 trst_pwron;
18 u32 cke_inactive;
19 u8 wrlat;
20 u8 caslat_lin;
21 u8 trc;
22 u8 trrd;
23 u8 tccd;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]24 u8 tbst_int_interval;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]25 u8 tfaw;
26 u8 trp;
27 u8 twtr;
28 u8 tras_min;
29 u8 tmrd;
30 u8 trtp;
31 u32 tras_max;
32 u8 tmod;
33 u8 tckesr;
34 u8 tcke;
35 u8 trcd_int;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]36 u8 tras_lockout;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]37 u8 tdal;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]38 u8 bstlen;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]39 u16 tdll;
40 u8 trp_ab;
41 u16 tref;
42 u8 trfc;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]43 u16 tref_int;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]44 u8 tpdex;
45 u8 txpdll;
46 u8 txsnr;
47 u16 txsr;
48 u8 cksrx;
49 u8 cksre;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]50 u8 freq_chg_en;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]51 u16 zqcl;
52 u16 zqinit;
53 u8 zqcs;
54 u8 ref_per_zq;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]55 u8 zqcs_rotate;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]56 u8 aprebit;
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]57 u8 cmd_age_cnt;
58 u8 age_cnt;
59 u8 q_fullness;
60 u8 odt_rd_mapcs0;
61 u8 odt_wr_mapcs0;
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]62 u8 wlmrd;
63 u8 wldqsen;
64};
65
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]66struct ddrmc_cr_setting {
67 u32 setting;
68 int cr_rnum; /* CR register ; -1 for last entry */
69};
70
71struct ddrmc_phy_setting {
72 u32 setting;
73 int phy_rnum; /* PHY register ; -1 for last entry */
74};
75
76void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]77void ddrmc_phy_init(void);
78void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
Albert ARIBAUD \\(3ADEV\\)25ac8ce2015-09-21 22:43:37 +0200[diff] [blame]79 struct ddrmc_cr_setting *board_cr_settings,
80 struct ddrmc_phy_setting *board_phy_settings,
81 int col_diff, int row_diff);
Sanchayan Maitye3a76e22015-04-15 16:24:22 +0530[diff] [blame]82
83#endif