| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Technologies, Inc. SM8550 TLMM block |
| 8 | |
| 9 | maintainers: |
| 10 | - Abel Vesa <abel.vesa@linaro.org> |
| 11 | |
| 12 | description: |
| 13 | Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC. |
| 14 | |
| 15 | allOf: |
| 16 | - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# |
| 17 | |
| 18 | properties: |
| 19 | compatible: |
| 20 | const: qcom,sm8550-tlmm |
| 21 | |
| 22 | reg: |
| 23 | maxItems: 1 |
| 24 | |
| 25 | interrupts: true |
| 26 | interrupt-controller: true |
| 27 | "#interrupt-cells": true |
| 28 | gpio-controller: true |
| 29 | |
| 30 | gpio-reserved-ranges: |
| 31 | minItems: 1 |
| 32 | maxItems: 105 |
| 33 | |
| 34 | gpio-line-names: |
| 35 | maxItems: 210 |
| 36 | |
| 37 | "#gpio-cells": true |
| 38 | gpio-ranges: true |
| 39 | wakeup-parent: true |
| 40 | |
| 41 | patternProperties: |
| 42 | "-state$": |
| 43 | oneOf: |
| 44 | - $ref: "#/$defs/qcom-sm8550-tlmm-state" |
| 45 | - patternProperties: |
| 46 | "-pins$": |
| 47 | $ref: "#/$defs/qcom-sm8550-tlmm-state" |
| 48 | additionalProperties: false |
| 49 | |
| 50 | $defs: |
| 51 | qcom-sm8550-tlmm-state: |
| 52 | type: object |
| 53 | description: |
| 54 | Pinctrl node's client devices use subnodes for desired pin configuration. |
| 55 | Client device subnodes use below standard properties. |
| 56 | $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state |
| 57 | unevaluatedProperties: false |
| 58 | |
| 59 | properties: |
| 60 | pins: |
| 61 | description: |
| 62 | List of gpio pins affected by the properties specified in this |
| 63 | subnode. |
| 64 | items: |
| 65 | oneOf: |
| 66 | - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" |
| 67 | - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] |
| 68 | minItems: 1 |
| 69 | maxItems: 36 |
| 70 | |
| 71 | function: |
| 72 | description: |
| 73 | Specify the alternative function to be configured for the specified |
| 74 | pins. |
| 75 | enum: [ aon_cci, aoss_cti, atest_char, atest_usb, |
| 76 | audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, |
| 77 | cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl, |
| 78 | cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx, |
| 79 | coex_uart1_tx, coex_uart2_rx, coex_uart2_tx, |
| 80 | cri_trng, dbg_out_clk, ddr_bist_complete, |
| 81 | ddr_bist_fail, ddr_bist_start, ddr_bist_stop, |
| 82 | ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, |
| 83 | gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0, |
| 84 | i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, |
| 85 | i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, |
| 86 | i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, |
| 87 | i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, |
| 88 | ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out, |
| 89 | mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, |
| 90 | mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, |
| 91 | pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, |
| 92 | pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, |
| 93 | prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, |
| 94 | qlink0_enable, qlink0_request, qlink0_wmss, |
| 95 | qlink1_enable, qlink1_request, qlink1_wmss, |
| 96 | qlink2_enable, qlink2_request, qlink2_wmss, |
| 97 | qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, |
| 98 | qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, |
| 99 | qup1_se5, qup1_se6, qup1_se7, qup2_se0, |
| 100 | qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira, |
| 101 | qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb, |
| 102 | qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1, |
| 103 | qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, |
| 104 | qup2_se7, sd_write_protect, sdc40, sdc41, sdc42, |
| 105 | sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, |
| 106 | tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, |
| 107 | tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2, |
| 108 | tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, |
| 109 | uim0_clk, uim0_data, uim0_present, uim0_reset, |
| 110 | uim1_clk, uim1_data, uim1_present, uim1_reset, |
| 111 | usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ] |
| 112 | |
| 113 | required: |
| 114 | - pins |
| 115 | |
| 116 | required: |
| 117 | - compatible |
| 118 | - reg |
| 119 | |
| 120 | additionalProperties: false |
| 121 | |
| 122 | examples: |
| 123 | - | |
| 124 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 125 | tlmm: pinctrl@f100000 { |
| 126 | compatible = "qcom,sm8550-tlmm"; |
| 127 | reg = <0x0f100000 0x300000>; |
| 128 | gpio-controller; |
| 129 | #gpio-cells = <2>; |
| 130 | gpio-ranges = <&tlmm 0 0 211>; |
| 131 | interrupt-controller; |
| 132 | #interrupt-cells = <2>; |
| 133 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| 134 | |
| 135 | gpio-wo-state { |
| 136 | pins = "gpio1"; |
| 137 | function = "gpio"; |
| 138 | }; |
| 139 | |
| 140 | uart-w-state { |
| 141 | rx-pins { |
| 142 | pins = "gpio26"; |
| 143 | function = "qup2_se7"; |
| 144 | bias-pull-up; |
| 145 | }; |
| 146 | |
| 147 | tx-pins { |
| 148 | pins = "gpio27"; |
| 149 | function = "qup2_se7"; |
| 150 | bias-disable; |
| 151 | }; |
| 152 | }; |
| 153 | }; |
| 154 | ... |