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git01.mediatek.com / filogic / uboot / af8cbc3ccf60b9cbbb91eb58db84732c164e78ef / . / dts / upstream / Bindings / pinctrl / qcom,sdx65-tlmm.yaml
blob: 27319782d94be59fae12e8dfb49ec16ef73a271f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDX65 TLMM block
8
9maintainers:
10 - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
11
12description:
13 Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC.
14
15properties:
16 compatible:
17 const: qcom,sdx65-tlmm
18
19 reg:
20 maxItems: 1
21
22 interrupts:
23 maxItems: 1
24
25 interrupt-controller: true
26 "#interrupt-cells": true
27 gpio-controller: true
28 "#gpio-cells": true
29 gpio-ranges: true
30
31 gpio-reserved-ranges:
32 maxItems: 1
33
34patternProperties:
35 "-state$":
36 oneOf:
37 - $ref: "#/$defs/qcom-sdx65-tlmm-state"
38 - patternProperties:
39 "-pins$":
40 $ref: "#/$defs/qcom-sdx65-tlmm-state"
41 additionalProperties: false
42
43$defs:
44 qcom-sdx65-tlmm-state:
45 type: object
46 description:
47 Pinctrl node's client devices use subnodes for desired pin configuration.
48 Client device subnodes use below standard properties.
49 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
50 unevaluatedProperties: false
51
52 properties:
53 pins:
54 description:
55 List of gpio pins affected by the properties specified in this subnode.
56 items:
57 oneOf:
58 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
59 - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
60 minItems: 1
61 maxItems: 150
62
63 function:
64 description:
65 Specify the alternative function to be configured for the specified
66 pins. Functions are only valid for gpio pins.
67 enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
68 bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
69 qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
70 dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
71 blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
72 mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
73 atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
74 cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
75 pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
76 qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
77 qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
78 atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
79 atest_usb20, atest_char0, dac_calib10, qdss_stm10,
80 qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
81 blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
82 qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
83 qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
84 dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
85 qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
86 dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
87 dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
88 dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, pcie_clkreq,
89 dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
90 sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
91 qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
92 uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
93 blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
94 qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
95 blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
96 cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
97 blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
98 qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
99 isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
100 qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
101 sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
102 gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
103 qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
104 tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
105 qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
106 sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
107 sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
108 ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
109 blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
110 pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
111 qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
112 qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
113 gpio ]
114
115 required:
116 - pins
117
118allOf:
119 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
120
121required:
122 - compatible
123 - reg
124
125additionalProperties: false
126
127examples:
128 - |
129 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 tlmm: pinctrl@f100000 {
131 compatible = "qcom,sdx65-tlmm";
132 reg = <0x03000000 0xdc2000>;
133 gpio-controller;
134 #gpio-cells = <2>;
135 gpio-ranges = <&tlmm 0 0 109>;
136 interrupt-controller;
137 #interrupt-cells = <2>;
138 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
139
140 gpio-wo-subnode-state {
141 pins = "gpio1";
142 function = "gpio";
143 };
144
145 uart-w-subnodes-state {
146 rx-pins {
147 pins = "gpio4";
148 function = "blsp_uart1";
149 bias-pull-up;
150 };
151
152 tx-pins {
153 pins = "gpio5";
154 function = "blsp_uart1";
155 bias-disable;
156 };
157 };
158 };
159...