| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Synopsys Designware Mobile Storage Host Controller |
| 8 | |
| 9 | maintainers: |
| 10 | - Ulf Hansson <ulf.hansson@linaro.org> |
| 11 | - Jisheng Zhang <Jisheng.Zhang@synaptics.com> |
| 12 | |
| 13 | allOf: |
| 14 | - $ref: mmc-controller.yaml# |
| 15 | |
| 16 | properties: |
| 17 | compatible: |
| 18 | enum: |
| 19 | - rockchip,rk3568-dwcmshc |
| 20 | - rockchip,rk3588-dwcmshc |
| 21 | - snps,dwcmshc-sdhci |
| 22 | |
| 23 | reg: |
| 24 | maxItems: 1 |
| 25 | |
| 26 | interrupts: |
| 27 | maxItems: 1 |
| 28 | |
| 29 | clocks: |
| 30 | minItems: 1 |
| 31 | items: |
| 32 | - description: core clock |
| 33 | - description: bus clock for optional |
| 34 | - description: axi clock for rockchip specified |
| 35 | - description: block clock for rockchip specified |
| 36 | - description: timer clock for rockchip specified |
| 37 | |
| 38 | |
| 39 | clock-names: |
| 40 | minItems: 1 |
| 41 | items: |
| 42 | - const: core |
| 43 | - const: bus |
| 44 | - const: axi |
| 45 | - const: block |
| 46 | - const: timer |
| 47 | |
| 48 | resets: |
| 49 | maxItems: 5 |
| 50 | |
| 51 | reset-names: |
| 52 | items: |
| 53 | - const: core |
| 54 | - const: bus |
| 55 | - const: axi |
| 56 | - const: block |
| 57 | - const: timer |
| 58 | |
| 59 | rockchip,txclk-tapnum: |
| 60 | description: Specify the number of delay for tx sampling. |
| 61 | $ref: /schemas/types.yaml#/definitions/uint8 |
| 62 | |
| 63 | |
| 64 | required: |
| 65 | - compatible |
| 66 | - reg |
| 67 | - interrupts |
| 68 | - clocks |
| 69 | - clock-names |
| 70 | |
| 71 | unevaluatedProperties: false |
| 72 | |
| 73 | examples: |
| 74 | - | |
| 75 | mmc@fe310000 { |
| 76 | compatible = "rockchip,rk3568-dwcmshc"; |
| 77 | reg = <0xfe310000 0x10000>; |
| 78 | interrupts = <0 25 0x4>; |
| 79 | clocks = <&cru 17>, <&cru 18>, <&cru 19>, <&cru 20>, <&cru 21>; |
| 80 | clock-names = "core", "bus", "axi", "block", "timer"; |
| 81 | bus-width = <8>; |
| 82 | #address-cells = <1>; |
| 83 | #size-cells = <0>; |
| 84 | }; |
| 85 | - | |
| 86 | mmc@aa0000 { |
| 87 | compatible = "snps,dwcmshc-sdhci"; |
| 88 | reg = <0xaa000 0x1000>; |
| 89 | interrupts = <0 25 0x4>; |
| 90 | clocks = <&cru 17>, <&cru 18>; |
| 91 | clock-names = "core", "bus"; |
| 92 | bus-width = <8>; |
| 93 | #address-cells = <1>; |
| 94 | #size-cells = <0>; |
| 95 | }; |
| 96 | |
| 97 | ... |