| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/media/renesas,vsp1.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Renesas VSP Video Processing Engine |
| 8 | |
| 9 | maintainers: |
| 10 | - Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| 11 | |
| 12 | description: |
| 13 | The VSP is a video processing engine that supports up-/down-scaling, alpha |
| 14 | blending, color space conversion and various other image processing features. |
| 15 | It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs. |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | oneOf: |
| 20 | - enum: |
| 21 | - renesas,r9a07g044-vsp2 # RZ/G2L |
| 22 | - renesas,vsp1 # R-Car Gen2 and RZ/G1 |
| 23 | - renesas,vsp2 # R-Car Gen3 and RZ/G2 |
| 24 | - items: |
| 25 | - enum: |
| 26 | - renesas,r9a07g054-vsp2 # RZ/V2L |
| 27 | - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback |
| 28 | |
| 29 | reg: |
| 30 | maxItems: 1 |
| 31 | |
| 32 | interrupts: |
| 33 | maxItems: 1 |
| 34 | |
| 35 | clocks: true |
| 36 | clock-names: true |
| 37 | |
| 38 | power-domains: |
| 39 | maxItems: 1 |
| 40 | |
| 41 | resets: |
| 42 | maxItems: 1 |
| 43 | |
| 44 | renesas,fcp: |
| 45 | $ref: /schemas/types.yaml#/definitions/phandle |
| 46 | description: |
| 47 | A phandle referencing the FCP that handles memory accesses for the VSP. |
| 48 | |
| 49 | required: |
| 50 | - compatible |
| 51 | - reg |
| 52 | - interrupts |
| 53 | - clocks |
| 54 | - power-domains |
| 55 | - resets |
| 56 | |
| 57 | additionalProperties: false |
| 58 | |
| 59 | allOf: |
| 60 | - if: |
| 61 | properties: |
| 62 | compatible: |
| 63 | contains: |
| 64 | const: renesas,vsp1 |
| 65 | then: |
| 66 | properties: |
| 67 | renesas,fcp: false |
| 68 | else: |
| 69 | required: |
| 70 | - renesas,fcp |
| 71 | |
| 72 | - if: |
| 73 | properties: |
| 74 | compatible: |
| 75 | contains: |
| 76 | const: renesas,r9a07g044-vsp2 |
| 77 | then: |
| 78 | properties: |
| 79 | clocks: |
| 80 | items: |
| 81 | - description: Main clock |
| 82 | - description: Register access clock |
| 83 | - description: Video clock |
| 84 | clock-names: |
| 85 | items: |
| 86 | - const: aclk |
| 87 | - const: pclk |
| 88 | - const: vclk |
| 89 | required: |
| 90 | - clock-names |
| 91 | else: |
| 92 | properties: |
| 93 | clocks: |
| 94 | maxItems: 1 |
| 95 | clock-names: false |
| 96 | |
| 97 | examples: |
| 98 | # R8A7790 (R-Car H2) VSP1-S |
| 99 | - | |
| 100 | #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| 101 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 102 | #include <dt-bindings/power/r8a7790-sysc.h> |
| 103 | |
| 104 | vsp@fe928000 { |
| 105 | compatible = "renesas,vsp1"; |
| 106 | reg = <0xfe928000 0x8000>; |
| 107 | interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
| 108 | clocks = <&cpg CPG_MOD 131>; |
| 109 | power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; |
| 110 | resets = <&cpg 131>; |
| 111 | }; |
| 112 | |
| 113 | # R8A77951 (R-Car H3) VSP2-BC |
| 114 | - | |
| 115 | #include <dt-bindings/clock/renesas-cpg-mssr.h> |
| 116 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 117 | #include <dt-bindings/power/r8a7795-sysc.h> |
| 118 | |
| 119 | vsp@fe920000 { |
| 120 | compatible = "renesas,vsp2"; |
| 121 | reg = <0xfe920000 0x8000>; |
| 122 | interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; |
| 123 | clocks = <&cpg CPG_MOD 624>; |
| 124 | power-domains = <&sysc R8A7795_PD_A3VP>; |
| 125 | resets = <&cpg 624>; |
| 126 | |
| 127 | renesas,fcp = <&fcpvb1>; |
| 128 | }; |
| 129 | ... |