dts/upstream/Bindings/edac/aspeed-sdram-edac.txt

Aspeed BMC SoC EDAC node

The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
correction check).

The memory controller supports SECDED (single bit error correction, double bit
error detection) and single bit error auto scrubbing by reserving 8 bits for
every 64 bit word (effectively reducing available memory to 8/9).

Note, the bootloader must configure ECC mode in the memory controller.


Required properties:
- compatible: should be one of
	- "aspeed,ast2400-sdram-edac"
	- "aspeed,ast2500-sdram-edac"
	- "aspeed,ast2600-sdram-edac"
- reg:        sdram controller register set should be <0x1e6e0000 0x174>
- interrupts: should be AVIC interrupt #0


Example:

	edac: sdram@1e6e0000 {
		compatible = "aspeed,ast2500-sdram-edac";
		reg = <0x1e6e0000 0x174>;
		interrupts = <0>;
	};