| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/allwinner,sun9i-a80-deu.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Allwinner A80 Detail Enhancement Unit |
| 8 | |
| 9 | maintainers: |
| 10 | - Chen-Yu Tsai <wens@csie.org> |
| 11 | - Maxime Ripard <mripard@kernel.org> |
| 12 | |
| 13 | description: | |
| 14 | The DEU (Detail Enhancement Unit), found in the Allwinner A80 SoC, |
| 15 | can sharpen the display content in both luma and chroma channels. |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | const: allwinner,sun9i-a80-deu |
| 20 | |
| 21 | reg: |
| 22 | maxItems: 1 |
| 23 | |
| 24 | interrupts: |
| 25 | maxItems: 1 |
| 26 | |
| 27 | clocks: |
| 28 | items: |
| 29 | - description: The DEU interface clock |
| 30 | - description: The DEU module clock |
| 31 | - description: The DEU DRAM clock |
| 32 | |
| 33 | clock-names: |
| 34 | items: |
| 35 | - const: ahb |
| 36 | - const: mod |
| 37 | - const: ram |
| 38 | |
| 39 | resets: |
| 40 | maxItems: 1 |
| 41 | |
| 42 | ports: |
| 43 | $ref: /schemas/graph.yaml#/properties/ports |
| 44 | |
| 45 | properties: |
| 46 | port@0: |
| 47 | $ref: /schemas/graph.yaml#/properties/port |
| 48 | description: | |
| 49 | Input endpoints of the controller. |
| 50 | |
| 51 | port@1: |
| 52 | $ref: /schemas/graph.yaml#/properties/port |
| 53 | description: | |
| 54 | Output endpoints of the controller. |
| 55 | |
| 56 | required: |
| 57 | - port@0 |
| 58 | - port@1 |
| 59 | |
| 60 | required: |
| 61 | - compatible |
| 62 | - reg |
| 63 | - interrupts |
| 64 | - clocks |
| 65 | - clock-names |
| 66 | - resets |
| 67 | - ports |
| 68 | |
| 69 | additionalProperties: false |
| 70 | |
| 71 | examples: |
| 72 | - | |
| 73 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 74 | |
| 75 | #include <dt-bindings/clock/sun9i-a80-de.h> |
| 76 | #include <dt-bindings/reset/sun9i-a80-de.h> |
| 77 | |
| 78 | deu0: deu@3300000 { |
| 79 | compatible = "allwinner,sun9i-a80-deu"; |
| 80 | reg = <0x03300000 0x40000>; |
| 81 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 82 | clocks = <&de_clocks CLK_BUS_DEU0>, |
| 83 | <&de_clocks CLK_IEP_DEU0>, |
| 84 | <&de_clocks CLK_DRAM_DEU0>; |
| 85 | clock-names = "ahb", |
| 86 | "mod", |
| 87 | "ram"; |
| 88 | resets = <&de_clocks RST_DEU0>; |
| 89 | |
| 90 | ports { |
| 91 | #address-cells = <1>; |
| 92 | #size-cells = <0>; |
| 93 | |
| 94 | deu0_in: port@0 { |
| 95 | reg = <0>; |
| 96 | |
| 97 | deu0_in_fe0: endpoint { |
| 98 | remote-endpoint = <&fe0_out_deu0>; |
| 99 | }; |
| 100 | }; |
| 101 | |
| 102 | deu0_out: port@1 { |
| 103 | #address-cells = <1>; |
| 104 | #size-cells = <0>; |
| 105 | reg = <1>; |
| 106 | |
| 107 | deu0_out_be0: endpoint@0 { |
| 108 | reg = <0>; |
| 109 | remote-endpoint = <&be0_in_deu0>; |
| 110 | }; |
| 111 | |
| 112 | deu0_out_be1: endpoint@1 { |
| 113 | reg = <1>; |
| 114 | remote-endpoint = <&be1_in_deu0>; |
| 115 | }; |
| 116 | }; |
| 117 | }; |
| 118 | }; |
| 119 | |
| 120 | ... |