blob: ccc4851b1881dfbb94c88a1b5ef9b26dffebbebb [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Bin Menge9f5a792016-05-07 07:46:32 -07002/*
3 * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
Bin Menge9f5a792016-05-07 07:46:32 -07004 */
5
6#include <common.h>
Bin Mengebe78742016-06-17 02:13:14 -07007#include <cpu.h>
8#include <dm.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Heinrich Schuchardtec958062023-12-16 09:11:57 +010010#include <mapmem.h>
Simon Glass50461092020-04-08 16:57:35 -060011#include <acpi/acpi_s3.h>
Simon Glass858fed12020-04-08 16:57:36 -060012#include <acpi/acpi_table.h>
Bin Meng4c762a62017-04-21 07:24:29 -070013#include <asm/io.h>
Bin Menge9f5a792016-05-07 07:46:32 -070014#include <asm/tables.h>
Bin Mengebe78742016-06-17 02:13:14 -070015#include <asm/arch/global_nvs.h>
Bin Menge9f5a792016-05-07 07:46:32 -070016#include <asm/arch/iomap.h>
Simon Glass50461092020-04-08 16:57:35 -060017#include <dm/uclass-internal.h>
Bin Menge9f5a792016-05-07 07:46:32 -070018
Simon Glass9bd6b622023-09-01 11:27:09 -060019static int baytrail_write_fadt(struct acpi_ctx *ctx,
20 const struct acpi_writer *entry)
Bin Menge9f5a792016-05-07 07:46:32 -070021{
Simon Glass9bd6b622023-09-01 11:27:09 -060022 struct acpi_table_header *header;
23 struct acpi_fadt *fadt;
24
25 fadt = ctx->current;
26 header = &fadt->header;
Bin Menge9f5a792016-05-07 07:46:32 -070027 u16 pmbase = ACPI_BASE_ADDRESS;
28
Simon Glass9bd6b622023-09-01 11:27:09 -060029 memset(fadt, '\0', sizeof(struct acpi_fadt));
Bin Menge9f5a792016-05-07 07:46:32 -070030
31 acpi_fill_header(header, "FACP");
32 header->length = sizeof(struct acpi_fadt);
33 header->revision = 4;
34
Bin Menge9f5a792016-05-07 07:46:32 -070035 fadt->preferred_pm_profile = ACPI_PM_MOBILE;
36 fadt->sci_int = 9;
37 fadt->smi_cmd = 0;
38 fadt->acpi_enable = 0;
39 fadt->acpi_disable = 0;
40 fadt->s4bios_req = 0;
41 fadt->pstate_cnt = 0;
42 fadt->pm1a_evt_blk = pmbase;
43 fadt->pm1b_evt_blk = 0x0;
44 fadt->pm1a_cnt_blk = pmbase + 0x4;
45 fadt->pm1b_cnt_blk = 0x0;
46 fadt->pm2_cnt_blk = pmbase + 0x50;
47 fadt->pm_tmr_blk = pmbase + 0x8;
48 fadt->gpe0_blk = pmbase + 0x20;
49 fadt->gpe1_blk = 0;
50 fadt->pm1_evt_len = 4;
51 fadt->pm1_cnt_len = 2;
52 fadt->pm2_cnt_len = 1;
53 fadt->pm_tmr_len = 4;
54 fadt->gpe0_blk_len = 8;
55 fadt->gpe1_blk_len = 0;
56 fadt->gpe1_base = 0;
57 fadt->cst_cnt = 0;
58 fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
59 fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
60 fadt->flush_size = 0;
61 fadt->flush_stride = 0;
62 fadt->duty_offset = 1;
63 fadt->duty_width = 0;
64 fadt->day_alrm = 0x0d;
65 fadt->mon_alrm = 0x00;
66 fadt->century = 0x00;
67 fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
68 fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
69 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
70 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
71 ACPI_FADT_PLATFORM_CLOCK;
72
73 fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
74 fadt->reset_reg.bit_width = 8;
75 fadt->reset_reg.bit_offset = 0;
76 fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
77 fadt->reset_reg.addrl = IO_PORT_RESET;
78 fadt->reset_reg.addrh = 0;
Bin Meng62e16c52017-08-28 22:09:11 -070079 fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
Bin Menge9f5a792016-05-07 07:46:32 -070080
Heinrich Schuchardtec958062023-12-16 09:11:57 +010081 fadt->x_firmware_ctrl = map_to_sysmem(ctx->facs);
82 fadt->x_dsdt = map_to_sysmem(ctx->dsdt);
Bin Menge9f5a792016-05-07 07:46:32 -070083
84 fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
85 fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
86 fadt->x_pm1a_evt_blk.bit_offset = 0;
87 fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
88 fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
89 fadt->x_pm1a_evt_blk.addrh = 0x0;
90
91 fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
92 fadt->x_pm1b_evt_blk.bit_width = 0;
93 fadt->x_pm1b_evt_blk.bit_offset = 0;
94 fadt->x_pm1b_evt_blk.access_size = 0;
95 fadt->x_pm1b_evt_blk.addrl = 0x0;
96 fadt->x_pm1b_evt_blk.addrh = 0x0;
97
98 fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
99 fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
100 fadt->x_pm1a_cnt_blk.bit_offset = 0;
101 fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
102 fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
103 fadt->x_pm1a_cnt_blk.addrh = 0x0;
104
105 fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
106 fadt->x_pm1b_cnt_blk.bit_width = 0;
107 fadt->x_pm1b_cnt_blk.bit_offset = 0;
108 fadt->x_pm1b_cnt_blk.access_size = 0;
109 fadt->x_pm1b_cnt_blk.addrl = 0x0;
110 fadt->x_pm1b_cnt_blk.addrh = 0x0;
111
112 fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
113 fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
114 fadt->x_pm2_cnt_blk.bit_offset = 0;
115 fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
116 fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
117 fadt->x_pm2_cnt_blk.addrh = 0x0;
118
119 fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
120 fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
121 fadt->x_pm_tmr_blk.bit_offset = 0;
122 fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
123 fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
124 fadt->x_pm_tmr_blk.addrh = 0x0;
125
126 fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
127 fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
128 fadt->x_gpe0_blk.bit_offset = 0;
129 fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
130 fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
131 fadt->x_gpe0_blk.addrh = 0x0;
132
133 fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
134 fadt->x_gpe1_blk.bit_width = 0;
135 fadt->x_gpe1_blk.bit_offset = 0;
136 fadt->x_gpe1_blk.access_size = 0;
137 fadt->x_gpe1_blk.addrl = 0x0;
138 fadt->x_gpe1_blk.addrh = 0x0;
139
140 header->checksum = table_compute_checksum(fadt, header->length);
Simon Glass9bd6b622023-09-01 11:27:09 -0600141
Andy Shevchenko6f15ab72023-09-01 11:27:10 -0600142 return acpi_add_fadt(ctx, fadt);
Bin Menge9f5a792016-05-07 07:46:32 -0700143}
Simon Glass9bd6b622023-09-01 11:27:09 -0600144ACPI_WRITER(5fadt, "FADT", baytrail_write_fadt, 0);
Bin Menge9f5a792016-05-07 07:46:32 -0700145
Simon Glass9ed41e72020-07-07 21:32:05 -0600146int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
Bin Mengebe78742016-06-17 02:13:14 -0700147{
148 struct udevice *dev;
149 int ret;
150
151 /* at least we have one processor */
152 gnvs->pcnt = 1;
153 /* override the processor count with actual number */
154 ret = uclass_find_first_device(UCLASS_CPU, &dev);
155 if (ret == 0 && dev != NULL) {
156 ret = cpu_get_count(dev);
157 if (ret > 0)
158 gnvs->pcnt = ret;
159 }
160
161 /* determine whether internal uart is on */
162 if (IS_ENABLED(CONFIG_INTERNAL_UART))
163 gnvs->iuart_en = 1;
164 else
165 gnvs->iuart_en = 0;
Simon Glass9ed41e72020-07-07 21:32:05 -0600166
167 return 0;
Bin Mengebe78742016-06-17 02:13:14 -0700168}
Bin Meng4c762a62017-04-21 07:24:29 -0700169
Bin Meng4c762a62017-04-21 07:24:29 -0700170/*
171 * The following two routines are called at a very early stage, even before
172 * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
173 * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
174 * of these two blocks are programmed by either U-Boot or FSP.
175 *
Simon Glass6c34fc12019-09-25 08:00:11 -0600176 * It has been verified that 1st phase API (see arch/x86/lib/fsp1/fsp_car.S)
Bin Meng4c762a62017-04-21 07:24:29 -0700177 * on Intel BayTrail SoC already initializes these two base addresses so
178 * we are safe to access these registers here.
179 */
180
181enum acpi_sleep_state chipset_prev_sleep_state(void)
182{
183 u32 pm1_sts;
184 u32 pm1_cnt;
185 u32 gen_pmcon1;
186 enum acpi_sleep_state prev_sleep_state = ACPI_S0;
187
188 /* Read Power State */
189 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
190 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
191 gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
192
193 debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
194 pm1_sts, pm1_cnt, gen_pmcon1);
195
196 if (pm1_sts & WAK_STS)
197 prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt);
198
199 if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
200 prev_sleep_state = ACPI_S5;
201
202 return prev_sleep_state;
203}
204
205void chipset_clear_sleep_state(void)
206{
207 u32 pm1_cnt;
208
209 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
210 outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
211}