blob: 83b8413097982a8bf591fcd9973a95d180b234cc [file] [log] [blame]
Luis Aranedac1c763d2018-07-24 11:31:19 -04001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2011 - 2015 Xilinx
4 * Copyright (C) 2012 National Instruments Corp.
5 */
6/dts-v1/;
7#include "zynq-7000.dtsi"
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11 model = "Digilent Zybo Z7 board";
12 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000";
13
14 aliases {
15 ethernet0 = &gem0;
16 serial0 = &uart1;
17 spi0 = &qspi;
18 mmc0 = &sdhci0;
19 };
20
21 memory@0 {
22 device_type = "memory";
23 reg = <0x0 0x40000000>;
24 };
25
26 chosen {
27 bootargs = "";
28 stdout-path = "serial0:115200n8";
29 };
30
31 gpio-leds {
32 compatible = "gpio-leds";
33
Michal Simek958c0e92020-11-26 14:25:02 +010034 led-ld4 {
Luis Aranedac1c763d2018-07-24 11:31:19 -040035 label = "zynq-zybo-z7:green:ld4";
36 gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
37 };
38 };
39
40 usb_phy0: phy0 {
41 #phy-cells = <0>;
42 compatible = "usb-nop-xceiv";
43 reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
44 };
45};
46
47&clkc {
48 ps-clk-frequency = <33333333>;
49};
50
51&gem0 {
52 status = "okay";
53 phy-mode = "rgmii-id";
54 phy-handle = <&ethernet_phy>;
55
56 ethernet_phy: ethernet-phy@0 {
57 reg = <0>;
58 device_type = "ethernet-phy";
59 };
60};
61
62&qspi {
Simon Glassd3a98cb2023-02-13 08:56:33 -070063 bootph-all;
Luis Aranedac1c763d2018-07-24 11:31:19 -040064 status = "okay";
65};
66
67&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070068 bootph-all;
Luis Aranedac1c763d2018-07-24 11:31:19 -040069 status = "okay";
70};
71
72&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070073 bootph-all;
Luis Aranedac1c763d2018-07-24 11:31:19 -040074 status = "okay";
75};
76
77&usb0 {
78 status = "okay";
79 dr_mode = "host";
80 usb-phy = <&usb_phy0>;
81};