Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / stm32f7-u-boot.dtsi
blob: efc4e2afe1517fb822326844f6acbd6250909337 [file] [log] [blame]
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
Patrice Chotard24dffa52019-02-19 16:49:05 +0100[diff] [blame]3#include <dt-bindings/memory/stm32-sdram.h>
Patrice Chotardcc4b0b02018-02-07 10:44:49 +0100[diff] [blame]4/{
5 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]6 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]7
8 fmc: fmc@A0000000 {
9 compatible = "st,stm32-fmc";
Patrice Chotardefb49c52021-11-15 11:39:16 +0100[diff] [blame]10 reg = <0xa0000000 0x1000>;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]11 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
12 pinctrl-0 = <&fmc_pins>;
13 pinctrl-names = "default";
14 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]15 bootph-all;
Patrice Chotardcc4b0b02018-02-07 10:44:49 +0100[diff] [blame]16 };
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]17
18 mac: ethernet@40028000 {
19 compatible = "st,stm32-dwmac";
20 reg = <0x40028000 0x8000>;
21 reg-names = "stmmaceth";
22 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
23 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
24 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
25 interrupts = <61>, <62>;
26 interrupt-names = "macirq", "eth_wake_irq";
27 snps,pbl = <8>;
28 snps,mixed-burst;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]29 pinctrl-0 = <&ethernet_mii>;
30 phy-mode = "rmii";
31 phy-handle = <&phy0>;
32
33 status = "okay";
34
35 mdio0 {
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "snps,dwmac-mdio";
39 phy0: ethernet-phy@0 {
40 reg = <0>;
41 };
42 };
43 };
44
Patrice Chotard62f56162020-11-06 08:11:58 +0100[diff] [blame]45 qspi: spi@A0001000 {
Patrice Chotardea75d102019-06-28 15:02:58 +0200[diff] [blame]46 compatible = "st,stm32f469-qspi";
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]47 #address-cells = <1>;
48 #size-cells = <0>;
Patrice Chotardefb49c52021-11-15 11:39:16 +0100[diff] [blame]49 reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]50 reg-names = "qspi", "qspi_mm";
51 interrupts = <92>;
52 spi-max-frequency = <108000000>;
53 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
54 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
55 pinctrl-0 = <&qspi_pins>;
56
57 status = "okay";
58 };
Patrice Chotardcc4b0b02018-02-07 10:44:49 +0100[diff] [blame]59 };
60};
61
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]62&clk_hse {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]64};
65
66&gpioa {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]68};
69
70&gpiob {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]72};
73
74&gpioc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]76};
77
78&gpiod {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]80};
81
82&gpioe {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]84};
85
86&gpiof {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]88};
89
90&gpiog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]92};
93
94&gpioh {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]96};
97
98&gpioi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]100};
101
Vikas Manocha3deae0d2017-04-12 14:16:36 -0700[diff] [blame]102&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]104
105 fmc_pins: fmc@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]107 pins
108 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]110 };
111 };
Vikas Manocha3deae0d2017-04-12 14:16:36 -0700[diff] [blame]112};
113
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]114&pwrcfg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-all;
Vikas Manocha3deae0d2017-04-12 14:16:36 -0700[diff] [blame]116};
Patrice Chotardb9574022017-11-15 13:14:43 +0100[diff] [blame]117
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]118&rcc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]119 bootph-all;
Patrice Chotardb9574022017-11-15 13:14:43 +0100[diff] [blame]120};
Patrice Chotarda60d3f82018-01-18 13:39:29 +0100[diff] [blame]121
Patrice Chotard83975322022-09-23 13:20:33 +0200[diff] [blame]122&timers5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-all;
Patrice Chotarddf2e02a2019-02-19 00:37:20 +0100[diff] [blame]124};
125
126&usart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]127 bootph-all;
Patrice Chotard555930a2019-02-18 23:19:45 +0100[diff] [blame]128 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
Patrice Chotarda60d3f82018-01-18 13:39:29 +0100[diff] [blame]129};