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git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / r8a779g0.dtsi
blob: 7a87a5dc1b6ad21907c2c658dec28ba55fcf745f [file] [log] [blame]
Phong Hoang7ffcd4a2023-02-28 22:37:04 +0100[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R-Car V4H (R8A779G0) SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/power/r8a779g0-sysc.h>
11
12/ {
13 compatible = "renesas,r8a779g0";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cluster0_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
20
21 opp-500000000 {
22 opp-hz = /bits/ 64 <500000000>;
23 opp-microvolt = <825000>;
24 clock-latency-ns = <500000>;
25 };
26 opp-1000000000 {
27 opp-hz = /bits/ 64 <1000000000>;
28 opp-microvolt = <825000>;
29 clock-latency-ns = <500000>;
30 };
31 opp-1500000000 {
32 opp-hz = /bits/ 64 <1500000000>;
33 opp-microvolt = <825000>;
34 clock-latency-ns = <500000>;
35 };
36 opp-1700000000 {
37 opp-hz = /bits/ 64 <1700000000>;
38 opp-microvolt = <825000>;
39 clock-latency-ns = <500000>;
40 opp-suspend;
41 };
42 opp-1800000000 {
43 opp-hz = /bits/ 64 <1800000000>;
44 opp-microvolt = <880000>;
45 clock-latency-ns = <500000>;
46 turbo-mode;
47 };
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu-map {
55 cluster0 {
56 core0 {
57 cpu = <&a76_0>;
58 };
59 core1 {
60 cpu = <&a76_1>;
61 };
62 };
63
64 cluster1 {
65 core0 {
66 cpu = <&a76_2>;
67 };
68 core1 {
69 cpu = <&a76_3>;
70 };
71 };
72 };
73
74 a76_0: cpu@0 {
75 compatible = "arm,cortex-a76";
76 reg = <0>;
77 device_type = "cpu";
78 power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
79 next-level-cache = <&L3_CA76_0>;
80 enable-method = "psci";
81 cpu-idle-states = <&CPU_SLEEP_0>;
82 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
83 operating-points-v2 = <&cluster0_opp>;
84 };
85
86 a76_1: cpu@100 {
87 compatible = "arm,cortex-a76";
88 reg = <0x100>;
89 device_type = "cpu";
90 power-domains = <&sysc R8A779G0_PD_A1E0D0C1>;
91 next-level-cache = <&L3_CA76_0>;
92 enable-method = "psci";
93 cpu-idle-states = <&CPU_SLEEP_0>;
94 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
95 operating-points-v2 = <&cluster0_opp>;
96 };
97
98 a76_2: cpu@10000 {
99 compatible = "arm,cortex-a76";
100 reg = <0x10000>;
101 device_type = "cpu";
102 power-domains = <&sysc R8A779G0_PD_A1E0D1C0>;
103 next-level-cache = <&L3_CA76_1>;
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
106 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
107 operating-points-v2 = <&cluster0_opp>;
108 };
109
110 a76_3: cpu@10100 {
111 compatible = "arm,cortex-a76";
112 reg = <0x10100>;
113 device_type = "cpu";
114 power-domains = <&sysc R8A779G0_PD_A1E0D1C1>;
115 next-level-cache = <&L3_CA76_1>;
116 enable-method = "psci";
117 cpu-idle-states = <&CPU_SLEEP_0>;
118 clocks = <&cpg CPG_CORE R8A779G0_CLK_Z0>;
119 operating-points-v2 = <&cluster0_opp>;
120 };
121
122 idle-states {
123 entry-method = "psci";
124
125 CPU_SLEEP_0: cpu-sleep-0 {
126 compatible = "arm,idle-state";
127 arm,psci-suspend-param = <0x0010000>;
128 local-timer-stop;
129 entry-latency-us = <400>;
130 exit-latency-us = <500>;
131 min-residency-us = <4000>;
132 };
133 };
134
135 L3_CA76_0: cache-controller-0 {
136 compatible = "cache";
137 power-domains = <&sysc R8A779G0_PD_A2E0D0>;
138 cache-unified;
139 cache-level = <3>;
140 };
141
142 L3_CA76_1: cache-controller-1 {
143 compatible = "cache";
144 power-domains = <&sysc R8A779G0_PD_A2E0D1>;
145 cache-unified;
146 cache-level = <3>;
147 };
148 };
149
150 psci {
151 compatible = "arm,psci-1.0", "arm,psci-0.2";
152 method = "smc";
153 };
154
155 extal_clk: extal {
156 compatible = "fixed-clock";
157 #clock-cells = <0>;
158 /* This value must be overridden by the board */
159 clock-frequency = <0>;
160 };
161
162 extalr_clk: extalr {
163 compatible = "fixed-clock";
164 #clock-cells = <0>;
165 /* This value must be overridden by the board */
166 clock-frequency = <0>;
167 };
168
169 pmu_a76 {
170 compatible = "arm,cortex-a76-pmu";
171 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
172 };
173
174 /* External SCIF clock - to be overridden by boards that provide it */
175 scif_clk: scif {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <0>;
179 };
180
181 soc: soc {
182 compatible = "simple-bus";
183 interrupt-parent = <&gic>;
184 #address-cells = <2>;
185 #size-cells = <2>;
186 ranges;
187
188 rwdt: watchdog@e6020000 {
189 compatible = "renesas,r8a779g0-wdt",
190 "renesas,rcar-gen4-wdt";
191 reg = <0 0xe6020000 0 0x0c>;
192 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&cpg CPG_MOD 907>;
194 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
195 resets = <&cpg 907>;
196 status = "disabled";
197 };
198
199 pfc: pinctrl@e6050000 {
200 compatible = "renesas,pfc-r8a779g0";
201 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
202 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
203 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
204 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>,
205 <0 0xe6068000 0 0x16c>;
206 };
207
208 gpio0: gpio@e6050180 {
209 compatible = "renesas,gpio-r8a779g0",
210 "renesas,rcar-gen4-gpio";
211 reg = <0 0xe6050180 0 0x54>;
212 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&cpg CPG_MOD 915>;
214 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
215 resets = <&cpg 915>;
216 gpio-controller;
217 #gpio-cells = <2>;
218 gpio-ranges = <&pfc 0 0 19>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 };
222
223 gpio1: gpio@e6050980 {
224 compatible = "renesas,gpio-r8a779g0",
225 "renesas,rcar-gen4-gpio";
226 reg = <0 0xe6050980 0 0x54>;
227 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cpg CPG_MOD 915>;
229 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
230 resets = <&cpg 915>;
231 gpio-controller;
232 #gpio-cells = <2>;
233 gpio-ranges = <&pfc 0 32 29>;
234 interrupt-controller;
235 #interrupt-cells = <2>;
236 };
237
238 gpio2: gpio@e6058180 {
239 compatible = "renesas,gpio-r8a779g0",
240 "renesas,rcar-gen4-gpio";
241 reg = <0 0xe6058180 0 0x54>;
242 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cpg CPG_MOD 916>;
244 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
245 resets = <&cpg 916>;
246 gpio-controller;
247 #gpio-cells = <2>;
248 gpio-ranges = <&pfc 0 64 20>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
251 };
252
253 gpio3: gpio@e6058980 {
254 compatible = "renesas,gpio-r8a779g0",
255 "renesas,rcar-gen4-gpio";
256 reg = <0 0xe6058980 0 0x54>;
257 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cpg CPG_MOD 916>;
259 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
260 resets = <&cpg 916>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 gpio-ranges = <&pfc 0 96 30>;
264 interrupt-controller;
265 #interrupt-cells = <2>;
266 };
267
268 gpio4: gpio@e6060180 {
269 compatible = "renesas,gpio-r8a779g0",
270 "renesas,rcar-gen4-gpio";
271 reg = <0 0xe6060180 0 0x54>;
272 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cpg CPG_MOD 917>;
274 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
275 resets = <&cpg 917>;
276 gpio-controller;
277 #gpio-cells = <2>;
278 gpio-ranges = <&pfc 0 128 25>;
279 interrupt-controller;
280 #interrupt-cells = <2>;
281 };
282
283 gpio5: gpio@e6060980 {
284 compatible = "renesas,gpio-r8a779g0",
285 "renesas,rcar-gen4-gpio";
286 reg = <0 0xe6060980 0 0x54>;
287 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&cpg CPG_MOD 917>;
289 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
290 resets = <&cpg 917>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 gpio-ranges = <&pfc 0 160 21>;
294 interrupt-controller;
295 #interrupt-cells = <2>;
296 };
297
298 gpio6: gpio@e6061180 {
299 compatible = "renesas,gpio-r8a779g0",
300 "renesas,rcar-gen4-gpio";
301 reg = <0 0xe6061180 0 0x54>;
302 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&cpg CPG_MOD 917>;
304 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
305 resets = <&cpg 917>;
306 gpio-controller;
307 #gpio-cells = <2>;
308 gpio-ranges = <&pfc 0 192 21>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 gpio7: gpio@e6061980 {
314 compatible = "renesas,gpio-r8a779g0",
315 "renesas,rcar-gen4-gpio";
316 reg = <0 0xe6061980 0 0x54>;
317 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 917>;
319 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
320 resets = <&cpg 917>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = <&pfc 0 224 21>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 };
327
328 gpio8: gpio@e6068180 {
329 compatible = "renesas,gpio-r8a779g0",
330 "renesas,rcar-gen4-gpio";
331 reg = <0 0xe6068180 0 0x54>;
332 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cpg CPG_MOD 918>;
334 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
335 resets = <&cpg 918>;
336 gpio-controller;
337 #gpio-cells = <2>;
338 gpio-ranges = <&pfc 0 256 14>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
341 };
342
343 cmt0: timer@e60f0000 {
344 compatible = "renesas,r8a779g0-cmt0",
345 "renesas,rcar-gen4-cmt0";
346 reg = <0 0xe60f0000 0 0x1004>;
347 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&cpg CPG_MOD 910>;
350 clock-names = "fck";
351 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
352 resets = <&cpg 910>;
353 status = "disabled";
354 };
355
356 cmt1: timer@e6130000 {
357 compatible = "renesas,r8a779g0-cmt1",
358 "renesas,rcar-gen4-cmt1";
359 reg = <0 0xe6130000 0 0x1004>;
360 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&cpg CPG_MOD 911>;
369 clock-names = "fck";
370 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
371 resets = <&cpg 911>;
372 status = "disabled";
373 };
374
375 cmt2: timer@e6140000 {
376 compatible = "renesas,r8a779g0-cmt1",
377 "renesas,rcar-gen4-cmt1";
378 reg = <0 0xe6140000 0 0x1004>;
379 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
383 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&cpg CPG_MOD 912>;
388 clock-names = "fck";
389 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
390 resets = <&cpg 912>;
391 status = "disabled";
392 };
393
394 cmt3: timer@e6148000 {
395 compatible = "renesas,r8a779g0-cmt1",
396 "renesas,rcar-gen4-cmt1";
397 reg = <0 0xe6148000 0 0x1004>;
398 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cpg CPG_MOD 913>;
407 clock-names = "fck";
408 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
409 resets = <&cpg 913>;
410 status = "disabled";
411 };
412
413 cpg: clock-controller@e6150000 {
414 compatible = "renesas,r8a779g0-cpg-mssr";
415 reg = <0 0xe6150000 0 0x4000>;
416 clocks = <&extal_clk>, <&extalr_clk>;
417 clock-names = "extal", "extalr";
418 #clock-cells = <2>;
419 #power-domain-cells = <0>;
420 #reset-cells = <1>;
421 };
422
423 rst: reset-controller@e6160000 {
424 compatible = "renesas,r8a779g0-rst";
425 reg = <0 0xe6160000 0 0x4000>;
426 };
427
428 sysc: system-controller@e6180000 {
429 compatible = "renesas,r8a779g0-sysc";
430 reg = <0 0xe6180000 0 0x4000>;
431 #power-domain-cells = <1>;
432 };
433
434 intc_ex: interrupt-controller@e61c0000 {
435 compatible = "renesas,intc-ex-r8a779g0", "renesas,irqc";
436 #interrupt-cells = <2>;
437 interrupt-controller;
438 reg = <0 0xe61c0000 0 0x200>;
439 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cpg CPG_MOD 611>;
446 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
447 resets = <&cpg 611>;
448 };
449
450 tmu0: timer@e61e0000 {
451 compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
452 reg = <0 0xe61e0000 0 0x30>;
453 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cpg CPG_MOD 713>;
457 clock-names = "fck";
458 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
459 resets = <&cpg 713>;
460 status = "disabled";
461 };
462
463 tmu1: timer@e6fc0000 {
464 compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
465 reg = <0 0xe6fc0000 0 0x30>;
466 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cpg CPG_MOD 714>;
470 clock-names = "fck";
471 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
472 resets = <&cpg 714>;
473 status = "disabled";
474 };
475
476 tmu2: timer@e6fd0000 {
477 compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
478 reg = <0 0xe6fd0000 0 0x30>;
479 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cpg CPG_MOD 715>;
483 clock-names = "fck";
484 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
485 resets = <&cpg 715>;
486 status = "disabled";
487 };
488
489 tmu3: timer@e6fe0000 {
490 compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
491 reg = <0 0xe6fe0000 0 0x30>;
492 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&cpg CPG_MOD 716>;
496 clock-names = "fck";
497 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
498 resets = <&cpg 716>;
499 status = "disabled";
500 };
501
502 tmu4: timer@ffc00000 {
503 compatible = "renesas,tmu-r8a779g0", "renesas,tmu";
504 reg = <0 0xffc00000 0 0x30>;
505 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 717>;
509 clock-names = "fck";
510 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
511 resets = <&cpg 717>;
512 status = "disabled";
513 };
514
515 i2c0: i2c@e6500000 {
516 compatible = "renesas,i2c-r8a779g0",
517 "renesas,rcar-gen4-i2c";
518 reg = <0 0xe6500000 0 0x40>;
519 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&cpg CPG_MOD 518>;
521 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
522 <&dmac1 0x91>, <&dmac1 0x90>;
523 dma-names = "tx", "rx", "tx", "rx";
524 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
525 resets = <&cpg 518>;
526 i2c-scl-internal-delay-ns = <110>;
527 #address-cells = <1>;
528 #size-cells = <0>;
529 status = "disabled";
530 };
531
532 i2c1: i2c@e6508000 {
533 compatible = "renesas,i2c-r8a779g0",
534 "renesas,rcar-gen4-i2c";
535 reg = <0 0xe6508000 0 0x40>;
536 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&cpg CPG_MOD 519>;
538 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
539 <&dmac1 0x93>, <&dmac1 0x92>;
540 dma-names = "tx", "rx", "tx", "rx";
541 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
542 resets = <&cpg 519>;
543 i2c-scl-internal-delay-ns = <110>;
544 #address-cells = <1>;
545 #size-cells = <0>;
546 status = "disabled";
547 };
548
549 i2c2: i2c@e6510000 {
550 compatible = "renesas,i2c-r8a779g0",
551 "renesas,rcar-gen4-i2c";
552 reg = <0 0xe6510000 0 0x40>;
553 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cpg CPG_MOD 520>;
555 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
556 <&dmac1 0x95>, <&dmac1 0x94>;
557 dma-names = "tx", "rx", "tx", "rx";
558 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
559 resets = <&cpg 520>;
560 i2c-scl-internal-delay-ns = <110>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 status = "disabled";
564 };
565
566 i2c3: i2c@e66d0000 {
567 compatible = "renesas,i2c-r8a779g0",
568 "renesas,rcar-gen4-i2c";
569 reg = <0 0xe66d0000 0 0x40>;
570 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cpg CPG_MOD 521>;
572 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
573 <&dmac1 0x97>, <&dmac1 0x96>;
574 dma-names = "tx", "rx", "tx", "rx";
575 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
576 resets = <&cpg 521>;
577 i2c-scl-internal-delay-ns = <110>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 status = "disabled";
581 };
582
583 i2c4: i2c@e66d8000 {
584 compatible = "renesas,i2c-r8a779g0",
585 "renesas,rcar-gen4-i2c";
586 reg = <0 0xe66d8000 0 0x40>;
587 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cpg CPG_MOD 522>;
589 dma-names = "tx", "rx", "tx", "rx";
590 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
591 <&dmac1 0x99>, <&dmac1 0x98>;
592 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
593 resets = <&cpg 522>;
594 i2c-scl-internal-delay-ns = <110>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 status = "disabled";
598 };
599
600 i2c5: i2c@e66e0000 {
601 compatible = "renesas,i2c-r8a779g0",
602 "renesas,rcar-gen4-i2c";
603 reg = <0 0xe66e0000 0 0x40>;
604 interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&cpg CPG_MOD 523>;
606 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
607 <&dmac1 0x9b>, <&dmac1 0x9a>;
608 dma-names = "tx", "rx", "tx", "rx";
609 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
610 resets = <&cpg 523>;
611 i2c-scl-internal-delay-ns = <110>;
612 #address-cells = <1>;
613 #size-cells = <0>;
614 status = "disabled";
615 };
616
617 hscif0: serial@e6540000 {
618 compatible = "renesas,hscif-r8a779g0",
619 "renesas,rcar-gen4-hscif", "renesas,hscif";
620 reg = <0 0xe6540000 0 0x60>;
621 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cpg CPG_MOD 514>,
623 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
624 <&scif_clk>;
625 clock-names = "fck", "brg_int", "scif_clk";
626 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
627 <&dmac1 0x31>, <&dmac1 0x30>;
628 dma-names = "tx", "rx", "tx", "rx";
629 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
630 resets = <&cpg 514>;
631 status = "disabled";
632 };
633
634 hscif1: serial@e6550000 {
635 compatible = "renesas,hscif-r8a779g0",
636 "renesas,rcar-gen4-hscif", "renesas,hscif";
637 reg = <0 0xe6550000 0 0x60>;
638 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&cpg CPG_MOD 515>,
640 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
641 <&scif_clk>;
642 clock-names = "fck", "brg_int", "scif_clk";
643 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
644 <&dmac1 0x33>, <&dmac1 0x32>;
645 dma-names = "tx", "rx", "tx", "rx";
646 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
647 resets = <&cpg 515>;
648 status = "disabled";
649 };
650
651 hscif2: serial@e6560000 {
652 compatible = "renesas,hscif-r8a779g0",
653 "renesas,rcar-gen4-hscif", "renesas,hscif";
654 reg = <0 0xe6560000 0 0x60>;
655 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&cpg CPG_MOD 516>,
657 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
658 <&scif_clk>;
659 clock-names = "fck", "brg_int", "scif_clk";
660 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
661 <&dmac1 0x35>, <&dmac1 0x34>;
662 dma-names = "tx", "rx", "tx", "rx";
663 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
664 resets = <&cpg 516>;
665 status = "disabled";
666 };
667
668 hscif3: serial@e66a0000 {
669 compatible = "renesas,hscif-r8a779g0",
670 "renesas,rcar-gen4-hscif", "renesas,hscif";
671 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
675 <&scif_clk>;
676 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
678 <&dmac1 0x37>, <&dmac1 0x36>;
679 dma-names = "tx", "rx", "tx", "rx";
680 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
681 resets = <&cpg 517>;
682 status = "disabled";
683 };
684
685 avb0: ethernet@e6800000 {
686 compatible = "renesas,etheravb-r8a779g0",
687 "renesas,etheravb-rcar-gen4";
688 reg = <0 0xe6800000 0 0x800>;
689 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
714 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
715 "ch5", "ch6", "ch7", "ch8", "ch9",
716 "ch10", "ch11", "ch12", "ch13",
717 "ch14", "ch15", "ch16", "ch17",
718 "ch18", "ch19", "ch20", "ch21",
719 "ch22", "ch23", "ch24";
720 clocks = <&cpg CPG_MOD 211>;
721 clock-names = "fck";
722 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
723 resets = <&cpg 211>;
724 phy-mode = "rgmii";
725 rx-internal-delay-ps = <0>;
726 tx-internal-delay-ps = <0>;
727 #address-cells = <1>;
728 #size-cells = <0>;
729 status = "disabled";
730 };
731
732 avb1: ethernet@e6810000 {
733 compatible = "renesas,etheravb-r8a779g0",
734 "renesas,etheravb-rcar-gen4";
735 reg = <0 0xe6810000 0 0x800>;
736 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
761 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
762 "ch5", "ch6", "ch7", "ch8", "ch9",
763 "ch10", "ch11", "ch12", "ch13",
764 "ch14", "ch15", "ch16", "ch17",
765 "ch18", "ch19", "ch20", "ch21",
766 "ch22", "ch23", "ch24";
767 clocks = <&cpg CPG_MOD 212>;
768 clock-names = "fck";
769 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
770 resets = <&cpg 212>;
771 phy-mode = "rgmii";
772 rx-internal-delay-ps = <0>;
773 tx-internal-delay-ps = <0>;
774 #address-cells = <1>;
775 #size-cells = <0>;
776 status = "disabled";
777 };
778
779 avb2: ethernet@e6820000 {
780 compatible = "renesas,etheravb-r8a779g0",
781 "renesas,etheravb-rcar-gen4";
782 reg = <0 0xe6820000 0 0x1000>;
783 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
794 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
808 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4",
809 "ch5", "ch6", "ch7", "ch8", "ch9",
810 "ch10", "ch11", "ch12", "ch13",
811 "ch14", "ch15", "ch16", "ch17",
812 "ch18", "ch19", "ch20", "ch21",
813 "ch22", "ch23", "ch24";
814 clocks = <&cpg CPG_MOD 213>;
815 clock-names = "fck";
816 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
817 resets = <&cpg 213>;
818 phy-mode = "rgmii";
819 rx-internal-delay-ps = <0>;
820 tx-internal-delay-ps = <0>;
821 #address-cells = <1>;
822 #size-cells = <0>;
823 status = "disabled";
824 };
825
826 pwm0: pwm@e6e30000 {
827 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
828 reg = <0 0xe6e30000 0 0x10>;
829 #pwm-cells = <2>;
830 clocks = <&cpg CPG_MOD 628>;
831 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
832 resets = <&cpg 628>;
833 status = "disabled";
834 };
835
836 pwm1: pwm@e6e31000 {
837 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
838 reg = <0 0xe6e31000 0 0x10>;
839 #pwm-cells = <2>;
840 clocks = <&cpg CPG_MOD 628>;
841 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
842 resets = <&cpg 628>;
843 status = "disabled";
844 };
845
846 pwm2: pwm@e6e32000 {
847 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
848 reg = <0 0xe6e32000 0 0x10>;
849 #pwm-cells = <2>;
850 clocks = <&cpg CPG_MOD 628>;
851 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
852 resets = <&cpg 628>;
853 status = "disabled";
854 };
855
856 pwm3: pwm@e6e33000 {
857 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
858 reg = <0 0xe6e33000 0 0x10>;
859 #pwm-cells = <2>;
860 clocks = <&cpg CPG_MOD 628>;
861 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
862 resets = <&cpg 628>;
863 status = "disabled";
864 };
865
866 pwm4: pwm@e6e34000 {
867 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
868 reg = <0 0xe6e34000 0 0x10>;
869 #pwm-cells = <2>;
870 clocks = <&cpg CPG_MOD 628>;
871 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
872 resets = <&cpg 628>;
873 status = "disabled";
874 };
875
876 pwm5: pwm@e6e35000 {
877 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
878 reg = <0 0xe6e35000 0 0x10>;
879 #pwm-cells = <2>;
880 clocks = <&cpg CPG_MOD 628>;
881 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
882 resets = <&cpg 628>;
883 status = "disabled";
884 };
885
886 pwm6: pwm@e6e36000 {
887 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
888 reg = <0 0xe6e36000 0 0x10>;
889 #pwm-cells = <2>;
890 clocks = <&cpg CPG_MOD 628>;
891 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
892 resets = <&cpg 628>;
893 status = "disabled";
894 };
895
896 pwm7: pwm@e6e37000 {
897 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
898 reg = <0 0xe6e37000 0 0x10>;
899 #pwm-cells = <2>;
900 clocks = <&cpg CPG_MOD 628>;
901 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
902 resets = <&cpg 628>;
903 status = "disabled";
904 };
905
906 pwm8: pwm@e6e38000 {
907 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
908 reg = <0 0xe6e38000 0 0x10>;
909 #pwm-cells = <2>;
910 clocks = <&cpg CPG_MOD 628>;
911 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
912 resets = <&cpg 628>;
913 status = "disabled";
914 };
915
916 pwm9: pwm@e6e39000 {
917 compatible = "renesas,pwm-r8a779g0", "renesas,pwm-rcar";
918 reg = <0 0xe6e39000 0 0x10>;
919 #pwm-cells = <2>;
920 clocks = <&cpg CPG_MOD 628>;
921 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
922 resets = <&cpg 628>;
923 status = "disabled";
924 };
925
926 scif0: serial@e6e60000 {
927 compatible = "renesas,scif-r8a779g0",
928 "renesas,rcar-gen4-scif", "renesas,scif";
929 reg = <0 0xe6e60000 0 64>;
930 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&cpg CPG_MOD 702>,
932 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
933 <&scif_clk>;
934 clock-names = "fck", "brg_int", "scif_clk";
935 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
936 <&dmac1 0x51>, <&dmac1 0x50>;
937 dma-names = "tx", "rx", "tx", "rx";
938 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
939 resets = <&cpg 702>;
940 status = "disabled";
941 };
942
943 scif1: serial@e6e68000 {
944 compatible = "renesas,scif-r8a779g0",
945 "renesas,rcar-gen4-scif", "renesas,scif";
946 reg = <0 0xe6e68000 0 64>;
947 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
948 clocks = <&cpg CPG_MOD 703>,
949 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
950 <&scif_clk>;
951 clock-names = "fck", "brg_int", "scif_clk";
952 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
953 <&dmac1 0x53>, <&dmac1 0x52>;
954 dma-names = "tx", "rx", "tx", "rx";
955 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
956 resets = <&cpg 703>;
957 status = "disabled";
958 };
959
960 scif3: serial@e6c50000 {
961 compatible = "renesas,scif-r8a779g0",
962 "renesas,rcar-gen4-scif", "renesas,scif";
963 reg = <0 0xe6c50000 0 64>;
964 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
965 clocks = <&cpg CPG_MOD 704>,
966 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
967 <&scif_clk>;
968 clock-names = "fck", "brg_int", "scif_clk";
969 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
970 <&dmac1 0x57>, <&dmac1 0x56>;
971 dma-names = "tx", "rx", "tx", "rx";
972 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
973 resets = <&cpg 704>;
974 status = "disabled";
975 };
976
977 scif4: serial@e6c40000 {
978 compatible = "renesas,scif-r8a779g0",
979 "renesas,rcar-gen4-scif", "renesas,scif";
980 reg = <0 0xe6c40000 0 64>;
981 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cpg CPG_MOD 705>,
983 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
984 <&scif_clk>;
985 clock-names = "fck", "brg_int", "scif_clk";
986 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
987 <&dmac1 0x59>, <&dmac1 0x58>;
988 dma-names = "tx", "rx", "tx", "rx";
989 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
990 resets = <&cpg 705>;
991 status = "disabled";
992 };
993
994 tpu: pwm@e6e80000 {
995 compatible = "renesas,tpu-r8a779g0", "renesas,tpu";
996 reg = <0 0xe6e80000 0 0x148>;
997 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&cpg CPG_MOD 718>;
999 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1000 resets = <&cpg 718>;
1001 #pwm-cells = <3>;
1002 status = "disabled";
1003 };
1004
1005 msiof0: spi@e6e90000 {
1006 compatible = "renesas,msiof-r8a779g0",
1007 "renesas,rcar-gen4-msiof";
1008 reg = <0 0xe6e90000 0 0x0064>;
1009 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cpg CPG_MOD 618>;
1011 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1012 <&dmac1 0x41>, <&dmac1 0x40>;
1013 dma-names = "tx", "rx", "tx", "rx";
1014 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1015 resets = <&cpg 618>;
1016 #address-cells = <1>;
1017 #size-cells = <0>;
1018 status = "disabled";
1019 };
1020
1021 msiof1: spi@e6ea0000 {
1022 compatible = "renesas,msiof-r8a779g0",
1023 "renesas,rcar-gen4-msiof";
1024 reg = <0 0xe6ea0000 0 0x0064>;
1025 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cpg CPG_MOD 619>;
1027 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1028 <&dmac1 0x43>, <&dmac1 0x42>;
1029 dma-names = "tx", "rx", "tx", "rx";
1030 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1031 resets = <&cpg 619>;
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1034 status = "disabled";
1035 };
1036
1037 msiof2: spi@e6c00000 {
1038 compatible = "renesas,msiof-r8a779g0",
1039 "renesas,rcar-gen4-msiof";
1040 reg = <0 0xe6c00000 0 0x0064>;
1041 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&cpg CPG_MOD 620>;
1043 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1044 <&dmac1 0x45>, <&dmac1 0x44>;
1045 dma-names = "tx", "rx", "tx", "rx";
1046 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1047 resets = <&cpg 620>;
1048 #address-cells = <1>;
1049 #size-cells = <0>;
1050 status = "disabled";
1051 };
1052
1053 msiof3: spi@e6c10000 {
1054 compatible = "renesas,msiof-r8a779g0",
1055 "renesas,rcar-gen4-msiof";
1056 reg = <0 0xe6c10000 0 0x0064>;
1057 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&cpg CPG_MOD 621>;
1059 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1060 <&dmac1 0x47>, <&dmac1 0x46>;
1061 dma-names = "tx", "rx", "tx", "rx";
1062 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1063 resets = <&cpg 621>;
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1066 status = "disabled";
1067 };
1068
1069 msiof4: spi@e6c20000 {
1070 compatible = "renesas,msiof-r8a779g0",
1071 "renesas,rcar-gen4-msiof";
1072 reg = <0 0xe6c20000 0 0x0064>;
1073 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1074 clocks = <&cpg CPG_MOD 622>;
1075 dmas = <&dmac0 0x49>, <&dmac0 0x48>,
1076 <&dmac1 0x49>, <&dmac1 0x48>;
1077 dma-names = "tx", "rx", "tx", "rx";
1078 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1079 resets = <&cpg 622>;
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1082 status = "disabled";
1083 };
1084
1085 msiof5: spi@e6c28000 {
1086 compatible = "renesas,msiof-r8a779g0",
1087 "renesas,rcar-gen4-msiof";
1088 reg = <0 0xe6c28000 0 0x0064>;
1089 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&cpg CPG_MOD 623>;
1091 dmas = <&dmac0 0x4b>, <&dmac0 0x4a>,
1092 <&dmac1 0x4b>, <&dmac1 0x4a>;
1093 dma-names = "tx", "rx", "tx", "rx";
1094 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1095 resets = <&cpg 623>;
1096 #address-cells = <1>;
1097 #size-cells = <0>;
1098 status = "disabled";
1099 };
1100
1101 dmac0: dma-controller@e7350000 {
1102 compatible = "renesas,dmac-r8a779g0",
1103 "renesas,rcar-gen4-dmac";
1104 reg = <0 0xe7350000 0 0x1000>,
1105 <0 0xe7300000 0 0x10000>;
1106 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1112 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1113 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1114 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1115 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1118 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1119 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1120 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1121 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1123 interrupt-names = "error",
1124 "ch0", "ch1", "ch2", "ch3", "ch4",
1125 "ch5", "ch6", "ch7", "ch8", "ch9",
1126 "ch10", "ch11", "ch12", "ch13",
1127 "ch14", "ch15";
1128 clocks = <&cpg CPG_MOD 709>;
1129 clock-names = "fck";
1130 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1131 resets = <&cpg 709>;
1132 #dma-cells = <1>;
1133 dma-channels = <16>;
1134 };
1135
1136 dmac1: dma-controller@e7351000 {
1137 compatible = "renesas,dmac-r8a779g0",
1138 "renesas,rcar-gen4-dmac";
1139 reg = <0 0xe7351000 0 0x1000>,
1140 <0 0xe7310000 0 0x10000>;
1141 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1158 interrupt-names = "error",
1159 "ch0", "ch1", "ch2", "ch3", "ch4",
1160 "ch5", "ch6", "ch7", "ch8", "ch9",
1161 "ch10", "ch11", "ch12", "ch13",
1162 "ch14", "ch15";
1163 clocks = <&cpg CPG_MOD 710>;
1164 clock-names = "fck";
1165 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1166 resets = <&cpg 710>;
1167 #dma-cells = <1>;
1168 dma-channels = <16>;
1169 };
1170
1171 mmc0: mmc@ee140000 {
1172 compatible = "renesas,sdhi-r8a779g0",
1173 "renesas,rcar-gen4-sdhi";
1174 reg = <0 0xee140000 0 0x2000>;
1175 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
1176 clocks = <&cpg CPG_MOD 706>,
1177 <&cpg CPG_CORE R8A779G0_CLK_SD0H>;
1178 clock-names = "core", "clkh";
1179 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1180 resets = <&cpg 706>;
1181 max-frequency = <200000000>;
1182 status = "disabled";
1183 };
1184
1185 rpc: spi@ee200000 {
1186 compatible = "renesas,r8a779g0-rpc-if",
1187 "renesas,rcar-gen4-rpc-if";
1188 reg = <0 0xee200000 0 0x200>,
1189 <0 0x08000000 0 0x04000000>,
1190 <0 0xee208000 0 0x100>;
1191 reg-names = "regs", "dirmap", "wbuf";
1192 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&cpg CPG_MOD 629>;
1194 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1195 resets = <&cpg 629>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198 status = "disabled";
1199 };
1200
1201 gic: interrupt-controller@f1000000 {
1202 compatible = "arm,gic-v3";
1203 #interrupt-cells = <3>;
1204 #address-cells = <0>;
1205 interrupt-controller;
1206 reg = <0x0 0xf1000000 0 0x20000>,
1207 <0x0 0xf1060000 0 0x110000>;
1208 interrupts = <GIC_PPI 9
1209 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1210 };
1211
1212 fcpvd0: fcp@fea10000 {
1213 compatible = "renesas,fcpv";
1214 reg = <0 0xfea10000 0 0x200>;
1215 clocks = <&cpg CPG_MOD 508>;
1216 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1217 resets = <&cpg 508>;
1218 };
1219
1220 fcpvd1: fcp@fea11000 {
1221 compatible = "renesas,fcpv";
1222 reg = <0 0xfea11000 0 0x200>;
1223 clocks = <&cpg CPG_MOD 509>;
1224 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1225 resets = <&cpg 509>;
1226 };
1227
1228 vspd0: vsp@fea20000 {
1229 compatible = "renesas,vsp2";
1230 reg = <0 0xfea20000 0 0x7000>;
1231 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&cpg CPG_MOD 830>;
1233 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1234 resets = <&cpg 830>;
1235
1236 renesas,fcp = <&fcpvd0>;
1237 };
1238
1239 vspd1: vsp@fea28000 {
1240 compatible = "renesas,vsp2";
1241 reg = <0 0xfea28000 0 0x7000>;
1242 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&cpg CPG_MOD 831>;
1244 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1245 resets = <&cpg 831>;
1246
1247 renesas,fcp = <&fcpvd1>;
1248 };
1249
1250 du: display@feb00000 {
1251 compatible = "renesas,du-r8a779g0";
1252 reg = <0 0xfeb00000 0 0x40000>;
1253 interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&cpg CPG_MOD 411>;
1256 clock-names = "du.0";
1257 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1258 resets = <&cpg 411>;
1259 reset-names = "du.0";
1260 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
1261
1262 status = "disabled";
1263
1264 ports {
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267
1268 port@0 {
1269 reg = <0>;
1270 du_out_dsi0: endpoint {
1271 remote-endpoint = <&dsi0_in>;
1272 };
1273 };
1274
1275 port@1 {
1276 reg = <1>;
1277 du_out_dsi1: endpoint {
1278 remote-endpoint = <&dsi1_in>;
1279 };
1280 };
1281 };
1282 };
1283
1284 dsi0: dsi-encoder@fed80000 {
1285 compatible = "renesas,r8a779g0-dsi-csi2-tx";
1286 reg = <0 0xfed80000 0 0x10000>;
1287 clocks = <&cpg CPG_MOD 415>,
1288 <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
1289 <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
1290 clock-names = "fck", "dsi", "pll";
1291 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1292 resets = <&cpg 415>;
1293
1294 status = "disabled";
1295
1296 ports {
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1299
1300 port@0 {
1301 reg = <0>;
1302 dsi0_in: endpoint {
1303 remote-endpoint = <&du_out_dsi0>;
1304 };
1305 };
1306
1307 port@1 {
1308 reg = <1>;
1309 };
1310 };
1311 };
1312
1313 dsi1: dsi-encoder@fed90000 {
1314 compatible = "renesas,r8a779g0-dsi-csi2-tx";
1315 reg = <0 0xfed90000 0 0x10000>;
1316 clocks = <&cpg CPG_MOD 416>,
1317 <&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
1318 <&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
1319 clock-names = "fck", "dsi", "pll";
1320 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
1321 resets = <&cpg 416>;
1322
1323 status = "disabled";
1324
1325 ports {
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1328
1329 port@0 {
1330 reg = <0>;
1331 dsi1_in: endpoint {
1332 remote-endpoint = <&du_out_dsi1>;
1333 };
1334 };
1335
1336 port@1 {
1337 reg = <1>;
1338 };
1339 };
1340 };
1341
1342 prr: chipid@fff00044 {
1343 compatible = "renesas,prr";
1344 reg = <0 0xfff00044 0 4>;
1345 };
1346 };
1347
1348 timer {
1349 compatible = "arm,armv8-timer";
1350 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1351 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1352 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1353 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1354 };
1355};