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git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / k3-j721s2-common-proc-board-u-boot.dtsi
blob: f940ffee8787286313d23907b6131ea19a8010e8 [file] [log] [blame]
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9409fb62023-07-22 00:14:36 +0530[diff] [blame]6#include "k3-j721s2-binman.dtsi"
7
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
13
14 aliases {
15 serial0 = &wkup_uart0;
16 serial1 = &mcu_uart0;
17 serial2 = &main_uart8;
18 i2c0 = &wkup_i2c0;
19 i2c1 = &mcu_i2c0;
20 i2c2 = &mcu_i2c1;
21 i2c3 = &main_i2c0;
22 ethernet0 = &cpsw_port1;
23 };
24};
25
26&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]28};
29
30&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]32};
33
34&main_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]36};
37
38&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]40
41 timer1: timer@40400000 {
42 compatible = "ti,omap5430-timer";
43 reg = <0x0 0x40400000 0x0 0x80>;
44 ti,timer-alwon;
Vignesh Raghavendra36a8b052022-03-07 14:55:51 +0530[diff] [blame]45 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]47 };
48
49 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]51 };
52};
53
54&mcu_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]56};
57
58&mcu_ringacc {
59 reg = <0x0 0x2b800000 0x0 0x400000>,
60 <0x0 0x2b000000 0x0 0x400000>,
61 <0x0 0x28590000 0x0 0x100>,
62 <0x0 0x2a500000 0x0 0x40000>,
63 <0x0 0x28440000 0x0 0x40000>;
64 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]66};
67
68&mcu_udmap {
69 reg = <0x0 0x285c0000 0x0 0x100>,
70 <0x0 0x284c0000 0x0 0x4000>,
71 <0x0 0x2a800000 0x0 0x40000>,
72 <0x0 0x284a0000 0x0 0x4000>,
73 <0x0 0x2aa00000 0x0 0x40000>,
74 <0x0 0x28400000 0x0 0x2000>;
75 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
76 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]78};
79
80&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]81 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]82};
83
84&sms {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]86 k3_sysreset: sysreset-controller {
87 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]89 };
90};
91
92&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]93 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]94};
95
96&main_uart8_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]98};
99
100&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]102};
103
104&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]106};
107
108&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]110};
111
112&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]114};
115
116&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]118};
119
120&main_uart8 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]122};
123
124&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]126};
127
128&wkup_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]130};
131
132&mcu_cpsw {
133 reg = <0x0 0x46000000 0x0 0x200000>,
134 <0x0 0x40f00200 0x0 0x8>;
135 reg-names = "cpsw_nuss", "mac_efuse";
136 /delete-property/ ranges;
137
138 cpsw-phy-sel@40f04040 {
139 compatible = "ti,am654-cpsw-phy-sel";
140 reg= <0x0 0x40f04040 0x0 0x4>;
141 reg-names = "gmii-sel";
142 };
143};
144
145&main_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]146 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]147};
148
149&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]150 bootph-pre-ram;
Aswath Govindraju26844212022-01-25 20:56:42 +0530[diff] [blame]151};