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git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / k3-j721e-sk-u-boot.dtsi
blob: 205dacff4da4a2657518ae17cf617236f5d8fa0e [file] [log] [blame]
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6#include <dt-bindings/net/ti-dp83867.h>
Neha Malcom Francis20a90042023-07-22 00:14:28 +0530[diff] [blame]7#include "k3-j721e-binman.dtsi"
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]8
9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 tick-timer = &timer1;
13 };
14
15 aliases {
16 ethernet0 = &cpsw_port1;
17 spi0 = &ospi0;
18 remoteproc0 = &mcu_r5fss0_core0;
19 remoteproc1 = &mcu_r5fss0_core1;
20 remoteproc2 = &main_r5fss0_core0;
21 remoteproc3 = &main_r5fss0_core1;
22 remoteproc4 = &main_r5fss1_core0;
23 remoteproc5 = &main_r5fss1_core1;
24 remoteproc6 = &c66_0;
25 remoteproc7 = &c66_1;
26 remoteproc8 = &c71_0;
27 i2c0 = &wkup_i2c0;
28 i2c1 = &mcu_i2c0;
29 i2c2 = &main_i2c0;
30 mmc1 = &main_sdhci1; /* SD Card */
31 };
32};
33
34&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]36
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]37 main_navss: bus@30000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]39 };
40};
41
42&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]44
45 timer1: timer@40400000 {
46 compatible = "ti,omap5430-timer";
47 reg = <0x0 0x40400000 0x0 0x80>;
48 ti,timer-alwon;
49 clock-frequency = <25000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]51 };
52
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]53 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]55
56 ringacc@2b800000 {
57 reg = <0x0 0x2b800000 0x0 0x400000>,
58 <0x0 0x2b000000 0x0 0x400000>,
59 <0x0 0x28590000 0x0 0x100>,
60 <0x0 0x2a500000 0x0 0x40000>,
61 <0x0 0x28440000 0x0 0x40000>;
62 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]64 };
65
66 dma-controller@285c0000 {
67 reg = <0x0 0x285c0000 0x0 0x100>,
68 <0x0 0x284c0000 0x0 0x4000>,
69 <0x0 0x2a800000 0x0 0x40000>,
70 <0x0 0x284a0000 0x0 0x4000>,
71 <0x0 0x2aa00000 0x0 0x40000>,
72 <0x0 0x28400000 0x0 0x2000>;
73 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
74 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]76 };
77 };
78
79 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]81 };
82};
83
84&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]86};
87
88&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]90 k3_sysreset: sysreset-controller {
91 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]93 };
94};
95
96&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]98};
99
100&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]101 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]102};
103
104&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]106};
107
108&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]110};
111
112&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]114};
115
116&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]118};
119
120&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]122};
123
124&main_sdhci0 {
125 status = "disabled";
126};
127
128&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]130};
131
132&wiz3_pll1_refclk {
133 assigned-clocks = <&wiz3_pll1_refclk>, <&wiz3_pll0_refclk>;
134 assigned-clock-parents = <&k3_clks 295 0>, <&k3_clks 295 9>;
135};
136
137&main_usbss0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]138 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]139};
140
141&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]142 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]143};
144
145&usb0 {
146 dr_mode = "host";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]148};
149
150&wiz2_pll1_refclk {
151 assigned-clocks = <&wiz2_pll1_refclk>, <&wiz2_pll0_refclk>;
152 assigned-clock-parents = <&k3_clks 294 0>, <&k3_clks 294 11>;
153};
154
155&main_usbss1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]156 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]157};
158
159&usbss1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]160 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]161};
162
163&usb1 {
164 dr_mode = "host";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]165 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]166};
167
168&mcu_cpsw {
169 reg = <0x0 0x46000000 0x0 0x200000>,
170 <0x0 0x40f00200 0x0 0x2>;
171 reg-names = "cpsw_nuss", "mac_efuse";
172 /delete-property/ ranges;
173
174 cpsw-phy-sel@40f04040 {
175 compatible = "ti,am654-cpsw-phy-sel";
176 reg= <0x0 0x40f04040 0x0 0x4>;
177 reg-names = "gmii-sel";
178 };
179};
180
181&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]182 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]183};
184
185&wkup_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]186 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]187};
188
189&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]190 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]191};
192
193&mcu_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]194 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]195};
196
197&mcu_i2c1 {
198 status = "disabled";
199};
200
201&main_i2c0 {
202 status = "disabled";
203};
204
205&main_i2c1 {
206 status = "disabled";
207};
208
209&main_i2c2 {
210 status = "disabled";
211};
212
213&main_i2c3 {
214 status = "disabled";
215};
216
217&main_i2c4 {
218 status = "disabled";
219};
220
221&main_i2c5 {
222 status = "disabled";
223};
224
225&main_i2c6 {
226 status = "disabled";
227};
228
229&mcu_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]230 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]231};
232
233&mcu_fss0_ospi0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]234 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]235};
236
237&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]238 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]239};
240
Sinthu Raja490d7162023-04-03 12:03:12 -0500[diff] [blame]241&hbmc {
242 status = "disabled";
243};
244
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]245&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]246 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]247
248 flash@0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]249 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]250
251 partition@3fc0000 {
252 label = "ospi.phypattern";
253 reg = <0x3fc0000 0x40000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]254 bootph-pre-ram;
Sinthu Raja65ed6a02022-02-09 15:06:55 +0530[diff] [blame]255 };
256 };
257};
258
259&serdes_ln_ctrl {
260 u-boot,mux-autoprobe;
261};
262
263&usb_serdes_mux {
264 u-boot,mux-autoprobe;
265};
266
267&pcie0_rc {
268 status = "disabled";
269};
270
271&pcie1_rc {
272 status = "disabled";
273};
274
275&pcie0_ep {
276 status = "disabled";
277};
278
279&pcie1_ep {
280 status = "disabled";
281};
282
283&dss {
284 status = "disabled";
285};