Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / k3-am654-r5-base-board-u-boot.dtsi
blob: 949320c91d0344a56f39379dd17b1ff5fcfd1345 [file] [log] [blame]
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2021 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6#include <dt-bindings/pinctrl/k3.h>
7#include <dt-bindings/net/ti-dp83867.h>
Neha Malcom Francis4ad962d2023-07-22 00:14:32 +0530[diff] [blame]8#include "k3-am65x-binman.dtsi"
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]9
10/ {
11 chosen {
12 stdout-path = "serial2:115200n8";
13 };
14
15 aliases {
16 serial2 = &main_uart0;
17 ethernet0 = &cpsw_port1;
18 usb0 = &usb0;
19 usb1 = &usb1;
20 spi0 = &ospi0;
21 spi1 = &ospi1;
22 };
23};
24
25&cbass_main{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]27 main_navss: bus@30800000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]29 };
30};
31
32&cbass_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]34
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]35 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]37
38 ringacc@2b800000 {
39 reg = <0x0 0x2b800000 0x0 0x400000>,
40 <0x0 0x2b000000 0x0 0x400000>,
41 <0x0 0x28590000 0x0 0x100>,
42 <0x0 0x2a500000 0x0 0x40000>,
43 <0x0 0x28440000 0x0 0x40000>;
44 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]46 ti,dma-ring-reset-quirk;
47 };
48
49 dma-controller@285c0000 {
50 reg = <0x0 0x285c0000 0x0 0x100>,
51 <0x0 0x284c0000 0x0 0x4000>,
52 <0x0 0x2a800000 0x0 0x40000>,
53 <0x0 0x284a0000 0x0 0x4000>,
54 <0x0 0x2aa00000 0x0 0x40000>,
55 <0x0 0x28400000 0x0 0x2000>;
56 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
57 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]59 };
60 };
61};
62
63&cbass_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]64 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]65
66 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]68 };
69};
70
71&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]73};
74
75&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]77 k3_sysreset: sysreset-controller {
78 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]80 };
81};
82
83&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]84 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]85};
86
87&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]89};
90
91&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]93};
94
95&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]97
98 wkup_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]100 };
101};
102
103&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]105 usb0_pins_default: usb0_pins_default {
106 pinctrl-single,pins = <
107 AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
108 >;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]110 };
111};
112
113&main_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]115};
116
117&main_pmx1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]119};
120
121&wkup_pmx0 {
122 mcu-fss0-ospi0-pins-default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]123 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]124 };
125};
126
127&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]129};
130
131&main_mmc0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]133};
134
135&main_mmc1_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]137};
138
139&sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]141};
142
143&sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]145};
146
147&davinci_mdio {
148 phy0: ethernet-phy@0 {
149 reg = <0>;
150 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
151 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
152 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
153 };
154};
155
156&mcu_cpsw {
157 reg = <0x0 0x46000000 0x0 0x200000>,
158 <0x0 0x40f00200 0x0 0x2>;
159 reg-names = "cpsw_nuss", "mac_efuse";
160 /delete-property/ ranges;
161
162 cpsw-phy-sel@40f04040 {
163 compatible = "ti,am654-cpsw-phy-sel";
164 reg= <0x0 0x40f04040 0x0 0x4>;
165 reg-names = "gmii-sel";
166 };
167};
168
169&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]170 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]171};
172
173&usb1 {
174 dr_mode = "peripheral";
175};
176
177&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]178 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]179};
180
181&ospi0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]182 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]183
184 flash@0{
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]185 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]186 };
187};
188
189&dwc3_0 {
190 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]191 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]192};
193
194&usb0_phy {
195 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]196 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]197};
198
199&usb0 {
200 pinctrl-names = "default";
201 pinctrl-0 = <&usb0_pins_default>;
Aswath Govindraju57c687b2022-05-18 16:49:12 +0530[diff] [blame]202 dr_mode = "peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]203 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]204};
205
206&scm_conf {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]207 bootph-pre-ram;
Lokesh Vutlaf6de8272021-06-22 12:04:29 +0530[diff] [blame]208};