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git01.mediatek.com / filogic / uboot / af6e2a784aed79dc58228f72dede8006c8e11da7 / . / arch / arm / dts / imx8mp-phyboard-pollux-rdk-u-boot.dtsi
blob: 1c7b2505499c4343d5ccbcd6b40de9c858448910 [file] [log] [blame]
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */
6
Teresa Remmet3e94fbd2021-07-07 12:57:57 +0000[diff] [blame]7#include "imx8mp-u-boot.dtsi"
8
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]9/ {
10 wdt-reboot {
11 compatible = "wdt-reboot";
12 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]13 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]14 };
15};
16
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]17&reg_usdhc2_vmmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]18 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]19};
20
Teresa Remmet5fc6abf2021-07-07 12:57:59 +0000[diff] [blame]21&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]22 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]23};
24
25&pinctrl_usdhc2_pins {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]27};
28
29&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]30 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]31};
32
33&pinctrl_usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]35};
36
Teresa Remmet44c5f682021-07-07 12:58:03 +0000[diff] [blame]37&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]38 bootph-pre-ram;
Teresa Remmet44c5f682021-07-07 12:58:03 +0000[diff] [blame]39};
40
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]41&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]42 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]43};
44
45&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]47};
48
49&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]50 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]51};
52
53&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]54 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]55};
56
57&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]59};
60
Teresa Remmet5fc6abf2021-07-07 12:57:59 +0000[diff] [blame]61&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]63};
64
65&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]66 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]67};
68
69&pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]71};
72
73&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]74 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]75};
76
77&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]78 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]79};
80
81&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Teresa Remmet30fb74d2021-01-13 16:28:09 +0100[diff] [blame]83};