| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /dts-v1/; |
| 3 | |
| 4 | #include <dt-bindings/interrupt-controller/irq.h> |
| 5 | #include <dt-bindings/interrupt-controller/mips-gic.h> |
| 6 | |
| 7 | /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */ |
| 8 | /memreserve/ 0x00001000 0x000ef000; /* YAMON */ |
| 9 | /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */ |
| 10 | |
| 11 | / { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | compatible = "mti,malta"; |
| 15 | |
| 16 | cpu_intc: interrupt-controller { |
| 17 | compatible = "mti,cpu-interrupt-controller"; |
| 18 | |
| 19 | interrupt-controller; |
| 20 | #interrupt-cells = <1>; |
| 21 | }; |
| 22 | |
| 23 | gic: interrupt-controller@1bdc0000 { |
| 24 | compatible = "mti,gic"; |
| 25 | reg = <0x1bdc0000 0x20000>; |
| 26 | |
| 27 | interrupt-controller; |
| 28 | #interrupt-cells = <3>; |
| 29 | |
| 30 | /* |
| 31 | * Declare the interrupt-parent even though the mti,gic |
| 32 | * binding doesn't require it, such that the kernel can |
| 33 | * figure out that cpu_intc is the root interrupt |
| 34 | * controller & should be probed first. |
| 35 | */ |
| 36 | interrupt-parent = <&cpu_intc>; |
| 37 | |
| 38 | timer { |
| 39 | compatible = "mti,gic-timer"; |
| 40 | interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; |
| 41 | }; |
| 42 | }; |
| 43 | |
| 44 | i8259: interrupt-controller@20 { |
| 45 | compatible = "intel,i8259"; |
| 46 | |
| 47 | interrupt-controller; |
| 48 | #interrupt-cells = <1>; |
| 49 | |
| 50 | interrupt-parent = <&gic>; |
| 51 | interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; |
| 52 | }; |
| 53 | |
| 54 | flash@1e000000 { |
| 55 | compatible = "intel,dt28f160", "cfi-flash"; |
| 56 | reg = <0x1e000000 0x400000>; |
| 57 | bank-width = <4>; |
| 58 | #address-cells = <1>; |
| 59 | #size-cells = <1>; |
| 60 | |
| 61 | partitions { |
| 62 | compatible = "fixed-partitions"; |
| 63 | #address-cells = <1>; |
| 64 | #size-cells = <1>; |
| 65 | |
| 66 | yamon@0 { |
| 67 | label = "YAMON"; |
| 68 | reg = <0x0 0x100000>; |
| 69 | read-only; |
| 70 | }; |
| 71 | |
| 72 | user-fs@100000 { |
| 73 | label = "User FS"; |
| 74 | reg = <0x100000 0x2e0000>; |
| 75 | }; |
| 76 | |
| 77 | board-config@3e0000 { |
| 78 | label = "Board Config"; |
| 79 | reg = <0x3e0000 0x20000>; |
| 80 | read-only; |
| 81 | }; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | fpga_regs: system-controller@1f000000 { |
| 86 | compatible = "mti,malta-fpga", "syscon", "simple-mfd"; |
| 87 | reg = <0x1f000000 0x1000>; |
| 88 | native-endian; |
| 89 | |
| 90 | lcd@410 { |
| 91 | compatible = "mti,malta-lcd"; |
| 92 | offset = <0x410>; |
| 93 | }; |
| 94 | |
| 95 | reboot { |
| 96 | compatible = "syscon-reboot"; |
| 97 | regmap = <&fpga_regs>; |
| 98 | offset = <0x500>; |
| 99 | mask = <0x42>; |
| 100 | }; |
| 101 | }; |
| 102 | |
| 103 | isa { |
| 104 | compatible = "isa"; |
| 105 | #address-cells = <2>; |
| 106 | #size-cells = <1>; |
| 107 | ranges = <1 0 0 0x1000>; |
| 108 | |
| 109 | rtc@70 { |
| 110 | compatible = "motorola,mc146818"; |
| 111 | reg = <1 0x70 0x8>; |
| 112 | |
| 113 | interrupt-parent = <&i8259>; |
| 114 | interrupts = <8>; |
| 115 | }; |
| 116 | }; |
| 117 | }; |