blob: a57ad45ed639d73929c2e5afd7f72eee2b4eed3f [file] [log] [blame]
Marcel Ziswiler36a439d2022-02-07 11:54:13 +01001// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2/*
3 * Copyright 2022 Toradex
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
15
16 wdt-reboot {
17 compatible = "wdt-reboot";
18 u-boot,dm-spl;
19 wdt = <&wdog1>;
20 };
21};
22
23&clk {
24 u-boot,dm-pre-reloc;
25 u-boot,dm-spl;
26 /delete-property/ assigned-clocks;
27 /delete-property/ assigned-clock-parents;
28 /delete-property/ assigned-clock-rates;
29
30};
31
32&eqos {
33 compatible = "fsl,imx-eqos";
34 /delete-property/ assigned-clocks;
35 /delete-property/ assigned-clock-parents;
36 /delete-property/ assigned-clock-rates;
37};
38
39&gpio1 {
40 u-boot,dm-spl;
41};
42
43&gpio2 {
44 u-boot,dm-spl;
45};
46
47&gpio3 {
48 u-boot,dm-spl;
49};
50
51&gpio4 {
52 u-boot,dm-spl;
53};
54
55&gpio5 {
56 u-boot,dm-spl;
57};
58
59&i2c1 {
60 u-boot,dm-spl;
61};
62
63&i2c2 {
64 u-boot,dm-spl;
65};
66
67&i2c3 {
68 u-boot,dm-spl;
69};
70
71&pinctrl_i2c1 {
72 u-boot,dm-spl;
73};
74
75&pinctrl_reg_usdhc2_vmmc {
76 u-boot,dm-spl;
77 u-boot,off-on-delay-us = <20000>;
78};
79
80&pinctrl_uart3 {
81 u-boot,dm-spl;
82};
83
84&pinctrl_usdhc2_gpio {
85 u-boot,dm-spl;
86};
87
88&pinctrl_usdhc2 {
89 u-boot,dm-spl;
90};
91
92&pinctrl_usdhc3 {
93 u-boot,dm-spl;
94};
95
96&pinctrl_wdog {
97 u-boot,dm-spl;
98};
99
100&pmic {
101 u-boot,dm-spl;
102};
103
104&reg_usdhc2_vmmc {
105 u-boot,dm-spl;
106};
107
108&uart3 {
109 u-boot,dm-spl;
110};
111
112&usdhc2 {
113 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
114 assigned-clock-rates = <400000000>;
115 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
116 sd-uhs-ddr50;
117 sd-uhs-sdr104;
118 u-boot,dm-spl;
119};
120
121&usdhc3 {
122 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
123 assigned-clock-rates = <400000000>;
124 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
125 mmc-hs400-1_8v;
126 mmc-hs400-enhanced-strobe;
127 u-boot,dm-spl;
128};
129
130&wdog1 {
131 u-boot,dm-spl;
132};