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git01.mediatek.com / filogic / uboot / af4b24a1679dc120d9f647b40a04c549d00d698d / . / dts / upstream / Bindings / timer / renesas,rz-mtu3.yaml
blob: 3931054b42fb97b2bb2ae575161f0337a5796c3d [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
8
9maintainers:
10 - Biju Das <biju.das.jz@bp.renesas.com>
11
12description: |
13 This hardware block consists of eight 16-bit timer channels and one
14 32-bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max
16 - Pulse input 3 lines
17 - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
18 for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
19 (when LWA = 1))
20 - Operating frequency Up to 100 MHz
21 - Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
22 - Waveform output on compare match
23 - Input capture function (noise filter setting available)
24 - Counter-clearing operation
25 - Simultaneous writing to multiple timer counters (TCNT)
26 (excluding MTU8)
27 - Simultaneous clearing on compare match or input capture
28 (excluding MTU8)
29 - Simultaneous input and output to registers in synchronization with
30 counter operations (excluding MTU8)
31 - Up to 12-phase PWM output in combination with synchronous operation
32 (excluding MTU8)
33 - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
34 - Buffer operation specifiable
35 - [MTU1, MTU2]
36 - Phase counting mode can be specified independently
37 - 32-bit phase counting mode can be specified for interlocked operation
38 of MTU1 and MTU2 (when TMDR3.LWA = 1)
39 - Cascade connection operation available
40 - [MTU3, MTU4, MTU6, and MTU7]
41 - Through interlocked operation of MTU3/4 and MTU6/7, the positive and
42 negative signals in six phases (12 phases in total) can be output in
43 complementary PWM and reset-synchronized PWM operation
44 - In complementary PWM mode, values can be transferred from buffer
45 registers to temporary registers at crests and troughs of the timer-
46 counter values or when the buffer registers (TGRD registers in MTU4
47 and MTU7) are written to
48 - Double-buffering selectable in complementary PWM mode
49 - [MTU3 and MTU4]
50 - Through interlocking with MTU0, a mode for driving AC synchronous
51 motors (brushless DC motors) by using complementary PWM output and
52 reset-synchronized PWM output is settable and allows the selection
53 of two types of waveform output (chopping or level)
54 - [MTU5]
55 - Capable of operation as a dead-time compensation counter
56 - [MTU0/MTU5, MTU1, MTU2, and MTU8]
57 - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
58 through interlocked operation with MTU0/MTU5 and MTU8
59 - Interrupt-skipping function
60 - In complementary PWM mode, interrupts on crests and troughs of counter
61 values and triggers to start conversion by the A/D converter can be
62 skipped
63 - Interrupt sources: 43 sources.
64 - Buffer operation:
65 - Automatic transfer of register data (transfer from the buffer
66 register to the timer register).
67 - Trigger generation
68 - A/D converter start triggers can be generated
69 - A/D converter start request delaying function enables A/D converter
70 to be started with any desired timing and to be synchronized with
71 PWM output
72 - Low power consumption function
73 - The MTU3a can be placed in the module-stop state
74
75 There are two phase counting modes. 16-bit phase counting mode in which
76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
77 counting mode in which MTU1 and MTU2 are cascaded.
78
79 In phase counting mode, the phase difference between two external input
80 clocks is detected and the corresponding TCNT is incremented or
81 decremented.
82 The below counters are supported
83 count0 - MTU1 16-bit phase counting
84 count1 - MTU2 16-bit phase counting
85 count2 - MTU1+ MTU2 32-bit phase counting
86
87 The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
88 complementary PWM mode{1,2,3}.
89
90 In complementary PWM mode, six positive-phase and six negative-phase PWM
91 waveforms (12 phases in total) with dead time can be output by
92 combining MTU{3,4} and MTU{6,7}.
93
94 The below pwm channels are supported in pwm mode 1.
95 pwm0 - MTU0.MTIOC0A PWM mode 1
96 pwm1 - MTU0.MTIOC0C PWM mode 1
97 pwm2 - MTU1.MTIOC1A PWM mode 1
98 pwm3 - MTU2.MTIOC2A PWM mode 1
99 pwm4 - MTU3.MTIOC3A PWM mode 1
100 pwm5 - MTU3.MTIOC3C PWM mode 1
101 pwm6 - MTU4.MTIOC4A PWM mode 1
102 pwm7 - MTU4.MTIOC4C PWM mode 1
103 pwm8 - MTU6.MTIOC6A PWM mode 1
104 pwm9 - MTU6.MTIOC6C PWM mode 1
105 pwm10 - MTU7.MTIOC7A PWM mode 1
106 pwm11 - MTU7.MTIOC7C PWM mode 1
107
108properties:
109 compatible:
110 items:
111 - enum:
112 - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five}
113 - renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
114 - renesas,r9a07g054-mtu3 # RZ/V2L
115 - const: renesas,rz-mtu3
116
117 reg:
118 maxItems: 1
119
120 interrupts:
121 items:
122 - description: MTU0.TGRA input capture/compare match
123 - description: MTU0.TGRB input capture/compare match
124 - description: MTU0.TGRC input capture/compare match
125 - description: MTU0.TGRD input capture/compare match
126 - description: MTU0.TCNT overflow
127 - description: MTU0.TGRE compare match
128 - description: MTU0.TGRF compare match
129 - description: MTU1.TGRA input capture/compare match
130 - description: MTU1.TGRB input capture/compare match
131 - description: MTU1.TCNT overflow
132 - description: MTU1.TCNT underflow
133 - description: MTU2.TGRA input capture/compare match
134 - description: MTU2.TGRB input capture/compare match
135 - description: MTU2.TCNT overflow
136 - description: MTU2.TCNT underflow
137 - description: MTU3.TGRA input capture/compare match
138 - description: MTU3.TGRB input capture/compare match
139 - description: MTU3.TGRC input capture/compare match
140 - description: MTU3.TGRD input capture/compare match
141 - description: MTU3.TCNT overflow
142 - description: MTU4.TGRA input capture/compare match
143 - description: MTU4.TGRB input capture/compare match
144 - description: MTU4.TGRC input capture/compare match
145 - description: MTU4.TGRD input capture/compare match
146 - description: MTU4.TCNT overflow/underflow
147 - description: MTU5.TGRU input capture/compare match
148 - description: MTU5.TGRV input capture/compare match
149 - description: MTU5.TGRW input capture/compare match
150 - description: MTU6.TGRA input capture/compare match
151 - description: MTU6.TGRB input capture/compare match
152 - description: MTU6.TGRC input capture/compare match
153 - description: MTU6.TGRD input capture/compare match
154 - description: MTU6.TCNT overflow
155 - description: MTU7.TGRA input capture/compare match
156 - description: MTU7.TGRB input capture/compare match
157 - description: MTU7.TGRC input capture/compare match
158 - description: MTU7.TGRD input capture/compare match
159 - description: MTU7.TCNT overflow/underflow
160 - description: MTU8.TGRA input capture/compare match
161 - description: MTU8.TGRB input capture/compare match
162 - description: MTU8.TGRC input capture/compare match
163 - description: MTU8.TGRD input capture/compare match
164 - description: MTU8.TCNT overflow
165 - description: MTU8.TCNT underflow
166
167 interrupt-names:
168 items:
169 - const: tgia0
170 - const: tgib0
171 - const: tgic0
172 - const: tgid0
173 - const: tciv0
174 - const: tgie0
175 - const: tgif0
176 - const: tgia1
177 - const: tgib1
178 - const: tciv1
179 - const: tciu1
180 - const: tgia2
181 - const: tgib2
182 - const: tciv2
183 - const: tciu2
184 - const: tgia3
185 - const: tgib3
186 - const: tgic3
187 - const: tgid3
188 - const: tciv3
189 - const: tgia4
190 - const: tgib4
191 - const: tgic4
192 - const: tgid4
193 - const: tciv4
194 - const: tgiu5
195 - const: tgiv5
196 - const: tgiw5
197 - const: tgia6
198 - const: tgib6
199 - const: tgic6
200 - const: tgid6
201 - const: tciv6
202 - const: tgia7
203 - const: tgib7
204 - const: tgic7
205 - const: tgid7
206 - const: tciv7
207 - const: tgia8
208 - const: tgib8
209 - const: tgic8
210 - const: tgid8
211 - const: tciv8
212 - const: tciu8
213
214 clocks:
215 maxItems: 1
216
217 power-domains:
218 maxItems: 1
219
220 resets:
221 maxItems: 1
222
223 "#pwm-cells":
224 const: 2
225
226required:
227 - compatible
228 - reg
229 - interrupts
230 - interrupt-names
231 - clocks
232 - power-domains
233 - resets
234
235additionalProperties: false
236
237examples:
238 - |
239 #include <dt-bindings/clock/r9a07g044-cpg.h>
240 #include <dt-bindings/interrupt-controller/arm-gic.h>
241
242 mtu3: timer@10001200 {
243 compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
244 reg = <0x10001200 0xb00>;
245 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
246 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
247 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
248 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
249 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
250 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
251 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
252 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
254 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
255 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
256 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
257 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
258 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
259 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
260 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
261 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
262 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
263 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
264 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
265 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
266 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
267 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
268 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
269 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
270 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
271 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
272 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
274 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
275 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
276 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
277 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
278 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
279 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
280 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
281 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
282 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
283 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
284 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
285 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
286 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
287 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
288 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
289 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",
290 "tgif0",
291 "tgia1", "tgib1", "tciv1", "tciu1",
292 "tgia2", "tgib2", "tciv2", "tciu2",
293 "tgia3", "tgib3", "tgic3", "tgid3", "tciv3",
294 "tgia4", "tgib4", "tgic4", "tgid4", "tciv4",
295 "tgiu5", "tgiv5", "tgiw5",
296 "tgia6", "tgib6", "tgic6", "tgid6", "tciv6",
297 "tgia7", "tgib7", "tgic7", "tgid7", "tciv7",
298 "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";
299 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
300 power-domains = <&cpg>;
301 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
302 #pwm-cells = <2>;
303 };