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git01.mediatek.com / filogic / uboot / aefb78d83db39fec9b81b44eccf277b218ccbfe0 / . / arch / arm / mach-uniphier / ph1-ld4 / pll_init.c
blob: f8ec2b61fb443d7fe57febd94da986b1b9c5556e [file] [log] [blame]
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]1/*
Masahiro Yamada663a23f2015-05-29 17:30:00 +0900[diff] [blame]2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
Masahiro Yamada663a23f2015-05-29 17:30:00 +0900[diff] [blame]8#include <linux/io.h>
Masahiro Yamada95387e22015-02-27 02:26:44 +0900[diff] [blame]9#include <mach/sc-regs.h>
10#include <mach/sg-regs.h>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]11
12#undef DPLL_SSC_RATE_1PER
13
Masahiro Yamadacfd171f2015-01-21 15:06:06 +0900[diff] [blame]14static void dpll_init(void)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]15{
16 u32 tmp;
17
18 /*
19 * Set Frequency
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT (DPLLCTRL.bit[29:20])
22 */
23 tmp = readl(SC_DPLLCTRL);
24 tmp &= ~0x000f0000;
25#if CONFIG_DDR_FREQ == 1600
26 tmp |= 0x000c0000;
27#elif CONFIG_DDR_FREQ == 1333
28 tmp |= 0x000d0000;
29#else
30# error "Unknown frequency"
31#endif
32
33#if defined(DPLL_SSC_RATE_1PER)
34 tmp &= ~SC_DPLLCTRL_SSC_RATE;
35#else
36 tmp |= SC_DPLLCTRL_SSC_RATE;
37#endif
38 writel(tmp, SC_DPLLCTRL);
39
40 tmp = readl(SC_DPLLCTRL2);
41 tmp |= SC_DPLLCTRL2_NRSTDS;
42 writel(tmp, SC_DPLLCTRL2);
43}
44
Masahiro Yamadacfd171f2015-01-21 15:06:06 +0900[diff] [blame]45static void upll_init(void)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]46{
47 u32 tmp, clk_mode_upll, clk_mode_axosel;
48
49 tmp = readl(SG_PINMON0);
50 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
51 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
52
53 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
54 tmp = readl(SC_UPLLCTRL);
55 tmp &= ~0x18000000;
56 writel(tmp, SC_UPLLCTRL);
57
58 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
59 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
60 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
61 /* AXO: 25MHz */
62 tmp &= ~0x07ffffff;
63 tmp |= 0x0228f5c0;
64 } else {
65 /* AXO: default 24.576MHz */
66 tmp &= ~0x07ffffff;
67 tmp |= 0x02328000;
68 }
69 }
70
71 writel(tmp, SC_UPLLCTRL);
72
73 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
74 tmp |= 0x08000000;
75 writel(tmp, SC_UPLLCTRL);
76
77 /* wait 10 usec */
78 udelay(10);
79
80 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
81 tmp |= 0x10000000;
82 writel(tmp, SC_UPLLCTRL);
83}
84
Masahiro Yamadacfd171f2015-01-21 15:06:06 +0900[diff] [blame]85static void vpll_init(void)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +0900[diff] [blame]86{
87 u32 tmp, clk_mode_axosel;
88
89 tmp = readl(SG_PINMON0);
90 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
91
92 /* set 1 to VPLA27WP and VPLA27WP */
93 tmp = readl(SC_VPLL27ACTRL);
94 tmp |= 0x00000001;
95 writel(tmp, SC_VPLL27ACTRL);
96 tmp = readl(SC_VPLL27BCTRL);
97 tmp |= 0x00000001;
98 writel(tmp, SC_VPLL27BCTRL);
99
100 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
101 tmp = readl(SC_VPLL27ACTRL3);
102 tmp &= ~0x10000000;
103 writel(tmp, SC_VPLL27ACTRL3);
104 tmp = readl(SC_VPLL27BCTRL3);
105 tmp &= ~0x10000000;
106 writel(tmp, SC_VPLL27BCTRL3);
107
108 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
109 tmp = readl(SC_VPLL27ACTRL2);
110 tmp &= ~0x10000000;
111 writel(tmp, SC_VPLL27ACTRL2);
112 tmp = readl(SC_VPLL27BCTRL2);
113 tmp &= ~0x10000000;
114 writel(tmp, SC_VPLL27BCTRL2);
115
116 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
117 tmp = readl(SC_VPLL27ACTRL2);
118 tmp &= ~0x0000007f;
119 tmp |= 0x00000020;
120 writel(tmp, SC_VPLL27ACTRL2);
121 tmp = readl(SC_VPLL27BCTRL2);
122 tmp &= ~0x0000007f;
123 tmp |= 0x00000020;
124 writel(tmp, SC_VPLL27BCTRL2);
125
126 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
127 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
128 /* AXO: 25MHz */
129 tmp = readl(SC_VPLL27ACTRL3);
130 tmp &= ~0x000fffff;
131 tmp |= 0x00066664;
132 writel(tmp, SC_VPLL27ACTRL3);
133 tmp = readl(SC_VPLL27BCTRL3);
134 tmp &= ~0x000fffff;
135 tmp |= 0x00066664;
136 writel(tmp, SC_VPLL27BCTRL3);
137 } else {
138 /* AXO: default 24.576MHz */
139 tmp = readl(SC_VPLL27ACTRL3);
140 tmp &= ~0x000fffff;
141 tmp |= 0x000f5800;
142 writel(tmp, SC_VPLL27ACTRL3);
143 tmp = readl(SC_VPLL27BCTRL3);
144 tmp &= ~0x000fffff;
145 tmp |= 0x000f5800;
146 writel(tmp, SC_VPLL27BCTRL3);
147 }
148
149 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
150 tmp = readl(SC_VPLL27ACTRL3);
151 tmp |= 0x10000000;
152 writel(tmp, SC_VPLL27ACTRL3);
153 tmp = readl(SC_VPLL27BCTRL3);
154 tmp |= 0x10000000;
155 writel(tmp, SC_VPLL27BCTRL3);
156
157 /* wait 10 usec */
158 udelay(10);
159
160 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
161 tmp = readl(SC_VPLL27ACTRL2);
162 tmp |= 0x10000000;
163 writel(tmp, SC_VPLL27ACTRL2);
164 tmp = readl(SC_VPLL27BCTRL2);
165 tmp |= 0x10000000;
166 writel(tmp, SC_VPLL27BCTRL2);
167
168 /* set 0 to VPLA27WP and VPLA27WP */
169 tmp = readl(SC_VPLL27ACTRL);
170 tmp &= ~0x00000001;
171 writel(tmp, SC_VPLL27ACTRL);
172 tmp = readl(SC_VPLL27BCTRL);
173 tmp |= ~0x00000001;
174 writel(tmp, SC_VPLL27BCTRL);
175}
176
177void pll_init(void)
178{
179 dpll_init();
180 upll_init();
181 vpll_init();
182
183 /*
184 * Wait 500 usec until dpll get stable
185 * We wait 10 usec in upll_init() and vpll_init()
186 * so 20 usec can be saved here.
187 */
188 udelay(480);
189}