| Jaehoon Chung | 7aff967 | 2012-10-15 19:10:31 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2012 SAMSUNG Electronics |
| 3 | * Jaehoon Chung <jh80.chung@samsung.com> |
| 4 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Jaehoon Chung | 7aff967 | 2012-10-15 19:10:31 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #define DWMCI_CLKSEL 0x09C |
| Jaehoon Chung | 7aff967 | 2012-10-15 19:10:31 +0000 | [diff] [blame] | 9 | #define DWMCI_SET_SAMPLE_CLK(x) (x) |
| 10 | #define DWMCI_SET_DRV_CLK(x) ((x) << 16) |
| 11 | #define DWMCI_SET_DIV_RATIO(x) ((x) << 24) |
| 12 | |
| Rajeshwari Shinde | 7016309 | 2013-10-29 12:53:13 +0530 | [diff] [blame] | 13 | #define EMMCP_MPSBEGIN0 0x1200 |
| 14 | #define EMMCP_SEND0 0x1204 |
| 15 | #define EMMCP_CTRL0 0x120C |
| 16 | |
| 17 | #define MPSCTRL_SECURE_READ_BIT (0x1<<7) |
| 18 | #define MPSCTRL_SECURE_WRITE_BIT (0x1<<6) |
| 19 | #define MPSCTRL_NON_SECURE_READ_BIT (0x1<<5) |
| 20 | #define MPSCTRL_NON_SECURE_WRITE_BIT (0x1<<4) |
| 21 | #define MPSCTRL_USE_FUSE_KEY (0x1<<3) |
| 22 | #define MPSCTRL_ECB_MODE (0x1<<2) |
| 23 | #define MPSCTRL_ENCRYPTION (0x1<<1) |
| 24 | #define MPSCTRL_VALID (0x1<<0) |
| 25 | |
| Rajeshwari S Shinde | ccfa20b | 2014-02-05 10:48:15 +0530 | [diff] [blame] | 26 | /* CLKSEL Register */ |
| 27 | #define DWMCI_DIVRATIO_BIT 24 |
| 28 | #define DWMCI_DIVRATIO_MASK 0x7 |
| 29 | |
| Amar | d850121 | 2013-04-27 11:42:55 +0530 | [diff] [blame] | 30 | int exynos_dwmmc_init(const void *blob); |
| Amar | d850121 | 2013-04-27 11:42:55 +0530 | [diff] [blame] | 31 | int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); |