blob: 69405d740b47dd39e9f84d3fba6a0e8b3046588a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glassdbc6e142016-03-16 07:44:37 -06002/*
3 * Copyright (c) 2016 Google, Inc
Simon Glassdbc6e142016-03-16 07:44:37 -06004 */
5
6#include <common.h>
7#include <dm.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Simon Glassdbc6e142016-03-16 07:44:37 -060010#include <syscon.h>
11#include <asm/cpu.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Simon Glassdbc6e142016-03-16 07:44:37 -060013#include <asm/gpio.h>
14#include <asm/intel_regs.h>
15#include <asm/mrc_common.h>
16#include <asm/pch_common.h>
17#include <asm/post.h>
18#include <asm/arch/me.h>
19#include <asm/report_platform.h>
20
21static const char *const ecc_decoder[] = {
22 "inactive",
23 "active on IO",
24 "disabled on IO",
25 "active"
26};
27
Pali Rohár4f4f5832022-09-09 17:32:40 +020028phys_size_t mrc_common_board_get_usable_ram_top(phys_size_t total_size)
Simon Glassdbc6e142016-03-16 07:44:37 -060029{
30 struct memory_info *info = &gd->arch.meminfo;
31 uintptr_t dest_addr = 0;
32 struct memory_area *largest = NULL;
33 int i;
34
35 /* Find largest area of memory below 4GB */
36
37 for (i = 0; i < info->num_areas; i++) {
38 struct memory_area *area = &info->area[i];
39
40 if (area->start >= 1ULL << 32)
41 continue;
42 if (!largest || area->size > largest->size)
43 largest = area;
44 }
45
46 /* If no suitable area was found, return an error. */
47 assert(largest);
48 if (!largest || largest->size < (2 << 20))
49 panic("No available memory found for relocation");
50
51 dest_addr = largest->start + largest->size;
52
Pali Rohár4f4f5832022-09-09 17:32:40 +020053 return (phys_size_t)dest_addr;
Simon Glassdbc6e142016-03-16 07:44:37 -060054}
55
56void mrc_common_dram_init_banksize(void)
57{
58 struct memory_info *info = &gd->arch.meminfo;
59 int num_banks;
60 int i;
61
62 for (i = 0, num_banks = 0; i < info->num_areas; i++) {
63 struct memory_area *area = &info->area[i];
64
65 if (area->start >= 1ULL << 32)
66 continue;
67 gd->bd->bi_dram[num_banks].start = area->start;
68 gd->bd->bi_dram[num_banks].size = area->size;
69 num_banks++;
70 }
71}
72
73int mrc_add_memory_area(struct memory_info *info, uint64_t start,
74 uint64_t end)
75{
76 struct memory_area *ptr;
77
78 if (info->num_areas == CONFIG_NR_DRAM_BANKS)
79 return -ENOSPC;
80
81 ptr = &info->area[info->num_areas];
82 ptr->start = start;
83 ptr->size = end - start;
84 info->total_memory += ptr->size;
85 if (ptr->start < (1ULL << 32))
86 info->total_32bit_memory += ptr->size;
87 debug("%d: memory %llx size %llx, total now %llx / %llx\n",
88 info->num_areas, ptr->start, ptr->size,
89 info->total_32bit_memory, info->total_memory);
90 info->num_areas++;
91
92 return 0;
93}
94
95/*
96 * Dump in the log memory controller configuration as read from the memory
97 * controller registers.
98 */
99void report_memory_config(void)
100{
101 u32 addr_decoder_common, addr_decode_ch[2];
102 int i;
103
104 addr_decoder_common = readl(MCHBAR_REG(0x5000));
105 addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
106 addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
107
108 debug("memcfg DDR3 clock %d MHz\n",
109 (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
110 debug("memcfg channel assignment: A: %d, B % d, C % d\n",
111 addr_decoder_common & 3,
112 (addr_decoder_common >> 2) & 3,
113 (addr_decoder_common >> 4) & 3);
114
115 for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
116 u32 ch_conf = addr_decode_ch[i];
117 debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
118 debug(" ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
119 debug(" enhanced interleave mode %s\n",
120 ((ch_conf >> 22) & 1) ? "on" : "off");
121 debug(" rank interleave %s\n",
122 ((ch_conf >> 21) & 1) ? "on" : "off");
123 debug(" DIMMA %d MB width x%d %s rank%s\n",
124 ((ch_conf >> 0) & 0xff) * 256,
125 ((ch_conf >> 19) & 1) ? 16 : 8,
126 ((ch_conf >> 17) & 1) ? "dual" : "single",
127 ((ch_conf >> 16) & 1) ? "" : ", selected");
128 debug(" DIMMB %d MB width x%d %s rank%s\n",
129 ((ch_conf >> 8) & 0xff) * 256,
130 ((ch_conf >> 20) & 1) ? 16 : 8,
131 ((ch_conf >> 18) & 1) ? "dual" : "single",
132 ((ch_conf >> 16) & 1) ? ", selected" : "");
133 }
134}
135
136int mrc_locate_spd(struct udevice *dev, int size, const void **spd_datap)
137{
138 const void *blob = gd->fdt_blob;
139 int spd_index;
140 struct gpio_desc desc[4];
141 int spd_node;
142 int node;
143 int ret;
144
145 ret = gpio_request_list_by_name(dev, "board-id-gpios", desc,
146 ARRAY_SIZE(desc), GPIOD_IS_IN);
147 if (ret < 0) {
148 debug("%s: gpio ret=%d\n", __func__, ret);
149 return ret;
150 }
151 spd_index = dm_gpio_get_values_as_int(desc, ret);
152 debug("spd index %d\n", spd_index);
153
Simon Glassdd79d6e2017-01-17 16:52:55 -0700154 node = fdt_first_subnode(blob, dev_of_offset(dev));
Simon Glassdbc6e142016-03-16 07:44:37 -0600155 if (node < 0)
156 return -EINVAL;
157 for (spd_node = fdt_first_subnode(blob, node);
158 spd_node > 0;
159 spd_node = fdt_next_subnode(blob, spd_node)) {
160 int len;
161
162 if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
163 continue;
164 *spd_datap = fdt_getprop(blob, spd_node, "data", &len);
165 if (len < size) {
166 printf("Missing SPD data\n");
167 return -EINVAL;
168 }
169
170 debug("Using SDRAM SPD data for '%s'\n",
171 fdt_get_name(blob, spd_node, NULL));
172 return 0;
173 }
174
175 printf("No SPD data found for index %d\n", spd_index);
176 return -ENOENT;
177}
178
179asmlinkage void sdram_console_tx_byte(unsigned char byte)
180{
181#ifdef DEBUG
182 putc(byte);
183#endif
184}
185
186/**
187 * Find the PEI executable in the ROM and execute it.
188 *
189 * @me_dev: Management Engine device
190 * @pei_data: configuration data for UEFI PEI reference code
191 */
192static int sdram_initialise(struct udevice *dev, struct udevice *me_dev,
193 void *pei_data, bool use_asm_linkage)
194{
195 unsigned version;
196 const char *data;
197
198 report_platform_info(dev);
199 debug("Starting UEFI PEI System Agent\n");
200
201 debug("PEI data at %p:\n", pei_data);
202
Tom Riniaefad5d2022-12-04 10:14:07 -0500203 data = (char *)CFG_X86_MRC_ADDR;
Simon Glassdbc6e142016-03-16 07:44:37 -0600204 if (data) {
205 int rv;
206 ulong start;
207
208 debug("Calling MRC at %p\n", data);
209 post_code(POST_PRE_MRC);
210 start = get_timer(0);
211 if (use_asm_linkage) {
212 asmlinkage int (*func)(void *);
213
214 func = (asmlinkage int (*)(void *))data;
215 rv = func(pei_data);
216 } else {
217 int (*func)(void *);
218
219 func = (int (*)(void *))data;
220 rv = func(pei_data);
221 }
222 post_code(POST_MRC);
223 if (rv) {
224 switch (rv) {
225 case -1:
226 printf("PEI version mismatch.\n");
227 break;
228 case -2:
229 printf("Invalid memory frequency.\n");
230 break;
231 default:
232 printf("MRC returned %x.\n", rv);
233 }
234 printf("Nonzero MRC return value.\n");
235 return -EFAULT;
236 }
237 debug("MRC execution time %lu ms\n", get_timer(start));
238 } else {
239 printf("UEFI PEI System Agent not found.\n");
240 return -ENOSYS;
241 }
242
243 version = readl(MCHBAR_REG(MCHBAR_PEI_VERSION));
244 debug("System Agent Version %d.%d.%d Build %d\n",
245 version >> 24 , (version >> 16) & 0xff,
246 (version >> 8) & 0xff, version & 0xff);
247
Simon Glassdbc6e142016-03-16 07:44:37 -0600248 return 0;
249}
250
251int mrc_common_init(struct udevice *dev, void *pei_data, bool use_asm_linkage)
252{
253 struct udevice *me_dev;
254 int ret;
255
256 ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
257 if (ret)
258 return ret;
259
260 ret = sdram_initialise(dev, me_dev, pei_data, use_asm_linkage);
261 if (ret)
262 return ret;
263 quick_ram_check();
264 post_code(POST_DRAM);
265 report_memory_config();
266
267 return 0;
268}