TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 1 | /* |
| 2 | * IO header file |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
Haiying Wang | c123a38 | 2007-02-21 16:52:31 +0100 | [diff] [blame] | 25 | |
TsiChungLiew | f4e17e1 | 2007-07-05 22:42:23 -0500 | [diff] [blame] | 26 | #ifndef __ASM_M68K_IO_H__ |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 27 | #define __ASM_M68K_IO_H__ |
| 28 | |
| 29 | #include <asm/byteorder.h> |
| 30 | |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 31 | #define readb(addr) in_8((volatile u8 *)(addr)) |
| 32 | #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 33 | #if !defined(__BIG_ENDIAN) |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 34 | #define readw(addr) (*(volatile u16 *) (addr)) |
| 35 | #define readl(addr) (*(volatile u32 *) (addr)) |
| 36 | #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) |
| 37 | #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 38 | #else |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 39 | #define readw(addr) in_le16((volatile u16 *)(addr)) |
| 40 | #define readl(addr) in_le32((volatile u32 *)(addr)) |
| 41 | #define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) |
| 42 | #define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 43 | #endif |
| 44 | |
| 45 | /* |
| 46 | * The insw/outsw/insl/outsl macros don't do byte-swapping. |
| 47 | * They are only used in practice for transferring buffers which |
| 48 | * are arrays of bytes, and byte-swapping is not appropriate in |
| 49 | * that case. - paulus |
| 50 | */ |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 51 | #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns)) |
| 52 | #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns)) |
| 53 | #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) |
| 54 | #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) |
| 55 | #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) |
| 56 | #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 57 | |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 58 | #define inb(port) in_8((u8 *)((port)+_IO_BASE)) |
| 59 | #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 60 | #if !defined(__BIG_ENDIAN) |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 61 | #define inw(port) in_be16((u16 *)((port)+_IO_BASE)) |
| 62 | #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val)) |
| 63 | #define inl(port) in_be32((u32 *)((port)+_IO_BASE)) |
| 64 | #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 65 | #else |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 66 | #define inw(port) in_le16((u16 *)((port)+_IO_BASE)) |
| 67 | #define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val)) |
| 68 | #define inl(port) in_le32((u32 *)((port)+_IO_BASE)) |
| 69 | #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 70 | #endif |
| 71 | |
| 72 | extern inline void _insb(volatile u8 * port, void *buf, int ns) |
| 73 | { |
| 74 | u8 *data = (u8 *) buf; |
| 75 | while (ns--) |
| 76 | *data++ = *port; |
| 77 | } |
| 78 | |
| 79 | extern inline void _outsb(volatile u8 * port, const void *buf, int ns) |
| 80 | { |
| 81 | u8 *data = (u8 *) buf; |
| 82 | while (ns--) |
| 83 | *port = *data++; |
| 84 | } |
| 85 | |
| 86 | extern inline void _insw(volatile u16 * port, void *buf, int ns) |
| 87 | { |
| 88 | u16 *data = (u16 *) buf; |
| 89 | while (ns--) |
| 90 | *data++ = __sw16(*port); |
| 91 | } |
| 92 | |
| 93 | extern inline void _outsw(volatile u16 * port, const void *buf, int ns) |
| 94 | { |
| 95 | u16 *data = (u16 *) buf; |
| 96 | while (ns--) { |
| 97 | *port = __sw16(*data); |
| 98 | data++; |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | extern inline void _insl(volatile u32 * port, void *buf, int nl) |
| 103 | { |
| 104 | u32 *data = (u32 *) buf; |
| 105 | while (nl--) |
| 106 | *data++ = __sw32(*port); |
| 107 | } |
| 108 | |
| 109 | extern inline void _outsl(volatile u32 * port, const void *buf, int nl) |
| 110 | { |
| 111 | u32 *data = (u32 *) buf; |
| 112 | while (nl--) { |
| 113 | *port = __sw32(*data); |
| 114 | data++; |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | extern inline void _insw_ns(volatile u16 * port, void *buf, int ns) |
| 119 | { |
| 120 | u16 *data = (u16 *) buf; |
| 121 | while (ns--) |
| 122 | *data++ = *port; |
| 123 | } |
| 124 | |
| 125 | extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns) |
| 126 | { |
| 127 | u16 *data = (u16 *) buf; |
| 128 | while (ns--) { |
| 129 | *port = *data++; |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | extern inline void _insl_ns(volatile u32 * port, void *buf, int nl) |
| 134 | { |
| 135 | u32 *data = (u32 *) buf; |
| 136 | while (nl--) |
| 137 | *data++ = *port; |
| 138 | } |
| 139 | |
| 140 | extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl) |
| 141 | { |
| 142 | u32 *data = (u32 *) buf; |
| 143 | while (nl--) { |
| 144 | *port = *data; |
| 145 | data++; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | /* |
| 150 | * The *_ns versions below don't do byte-swapping. |
| 151 | * Neither do the standard versions now, these are just here |
| 152 | * for older code. |
| 153 | */ |
TsiChungLiew | aedd3d7 | 2007-08-15 15:39:17 -0500 | [diff] [blame^] | 154 | #define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) |
| 155 | #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns)) |
| 156 | #define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) |
| 157 | #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl)) |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 158 | |
| 159 | #define IO_SPACE_LIMIT ~0 |
| 160 | |
| 161 | /* |
| 162 | * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. |
| 163 | */ |
| 164 | extern inline int in_8(volatile u8 * addr) |
| 165 | { |
| 166 | return (int)*addr; |
| 167 | } |
| 168 | |
| 169 | extern inline void out_8(volatile u8 * addr, int val) |
| 170 | { |
| 171 | *addr = (u8) val; |
| 172 | } |
| 173 | |
| 174 | extern inline int in_le16(volatile u16 * addr) |
| 175 | { |
| 176 | return __sw16(*addr); |
| 177 | } |
| 178 | |
| 179 | extern inline int in_be16(volatile u16 * addr) |
| 180 | { |
| 181 | return (*addr & 0xFFFF); |
| 182 | } |
| 183 | |
| 184 | extern inline void out_le16(volatile u16 * addr, int val) |
| 185 | { |
| 186 | *addr = __sw16(val); |
| 187 | } |
| 188 | |
| 189 | extern inline void out_be16(volatile u16 * addr, int val) |
| 190 | { |
| 191 | *addr = (u16) val; |
| 192 | } |
| 193 | |
| 194 | extern inline unsigned in_le32(volatile u32 * addr) |
| 195 | { |
| 196 | return __sw32(*addr); |
| 197 | } |
| 198 | |
| 199 | extern inline unsigned in_be32(volatile u32 * addr) |
| 200 | { |
| 201 | return (*addr); |
| 202 | } |
| 203 | |
| 204 | extern inline void out_le32(volatile unsigned *addr, int val) |
| 205 | { |
| 206 | *addr = __sw32(val); |
| 207 | } |
| 208 | |
| 209 | extern inline void out_be32(volatile unsigned *addr, int val) |
Haiying Wang | c123a38 | 2007-02-21 16:52:31 +0100 | [diff] [blame] | 210 | { |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 211 | *addr = val; |
Haiying Wang | c123a38 | 2007-02-21 16:52:31 +0100 | [diff] [blame] | 212 | } |
| 213 | |
TsiChungLiew | 54d7b34 | 2007-08-05 03:43:30 -0500 | [diff] [blame] | 214 | static inline void sync(void) |
| 215 | { |
| 216 | /* This sync function is for PowerPC or other architecture instruction |
| 217 | * ColdFire does not have this instruction. Dummy function, added for |
| 218 | * compatibility (CFI driver) |
| 219 | */ |
| 220 | } |
TsiChung Liew | f6afe72 | 2007-06-18 13:50:13 -0500 | [diff] [blame] | 221 | #endif /* __ASM_M68K_IO_H__ */ |