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git01.mediatek.com / filogic / uboot / aed3358b98e096f3c06a9a867a0cfa8b2564393b / . / include / asm-blackfin / arch-common / cdef_LPBlackfin.h
blob: 90b21e525baccd97891263d3a3fe556fc3b1c5e2 [file] [log] [blame]
Aubrey.Li9da597f2007-03-09 13:38:44 +0800[diff] [blame]1/************************************************************************
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]2 *
Aubrey.Li9da597f2007-03-09 13:38:44 +0800[diff] [blame]3 * cdef_LPBlackfin.h
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]4 *
Aubrey.Li9da597f2007-03-09 13:38:44 +0800[diff] [blame]5 * (c) Copyright 2002-2003 Analog Devices, Inc. All rights reserved.
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]6 *
Aubrey.Li9da597f2007-03-09 13:38:44 +0800[diff] [blame]7 ************************************************************************/
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]8
9#ifndef _CDEF_LPBLACKFIN_H
10#define _CDEF_LPBLACKFIN_H
11
Aubrey.Li9da597f2007-03-09 13:38:44 +0800[diff] [blame]12#if !defined(__ADSPLPBLACKFIN__)
13#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
14#endif
15#include <asm/arch-common/def_LPBlackfin.h>
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]16
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]17/* Cache & SRAM Memory */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]18#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
19#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
20#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
21#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]22#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
23#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
24#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
25#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
26#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
27#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
28#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
29#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
30#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
31#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
32#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
33#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
34#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
35#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
36#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
37#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
38#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
39#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
40#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
41#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
42#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
43#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
44#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
45#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
46#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
47#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
48#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
49#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
50#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
51#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
52#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
53#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
54#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]55#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
56#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]57#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
58#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
59#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
60#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
61#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
62#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
63#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
64#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
65#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
66#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
67#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
68#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
69#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
70#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
71#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
72#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
73#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
74#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
75#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
76#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
77#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
78#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
79#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
80#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
81#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
82#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
83#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
84#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
85#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
86#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
87#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
88#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
89#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
90#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
91#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
92#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]93#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
94#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
95
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]96/* Event/Interrupt Registers */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]97#define pEVT0 ((volatile void **)EVT0)
98#define pEVT1 ((volatile void **)EVT1)
99#define pEVT2 ((volatile void **)EVT2)
100#define pEVT3 ((volatile void **)EVT3)
101#define pEVT4 ((volatile void **)EVT4)
102#define pEVT5 ((volatile void **)EVT5)
103#define pEVT6 ((volatile void **)EVT6)
104#define pEVT7 ((volatile void **)EVT7)
105#define pEVT8 ((volatile void **)EVT8)
106#define pEVT9 ((volatile void **)EVT9)
107#define pEVT10 ((volatile void **)EVT10)
108#define pEVT11 ((volatile void **)EVT11)
109#define pEVT12 ((volatile void **)EVT12)
110#define pEVT13 ((volatile void **)EVT13)
111#define pEVT14 ((volatile void **)EVT14)
112#define pEVT15 ((volatile void **)EVT15)
113#define pIMASK ((volatile unsigned long *)IMASK)
114#define pIPEND ((volatile unsigned long *)IPEND)
115#define pILAT ((volatile unsigned long *)ILAT)
116
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]117/* Core Timer Registers */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]118#define pTCNTL ((volatile unsigned long *)TCNTL)
119#define pTPERIOD ((volatile unsigned long *)TPERIOD)
120#define pTSCALE ((volatile unsigned long *)TSCALE)
121#define pTCOUNT ((volatile unsigned long *)TCOUNT)
122
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]123/* Debug/MP/Emulation Registers */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]124#define pDSPID ((volatile unsigned long *)DSPID)
125#define pDBGCTL ((volatile unsigned long *)DBGCTL)
126#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
127#define pEMUDAT ((volatile unsigned long *)EMUDAT)
128
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]129/* Trace Buffer Registers */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]130#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
131#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
132#define pTBUF ((volatile void **)TBUF)
133
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]134/* Watch Point Control Registers */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]135#define pWPIACTL ((volatile unsigned long *)WPIACTL)
136#define pWPIA0 ((volatile void **)WPIA0)
137#define pWPIA1 ((volatile void **)WPIA1)
138#define pWPIA2 ((volatile void **)WPIA2)
139#define pWPIA3 ((volatile void **)WPIA3)
140#define pWPIA4 ((volatile void **)WPIA4)
141#define pWPIA5 ((volatile void **)WPIA5)
142#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
143#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
144#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
145#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
146#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
147#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
148#define pWPDACTL ((volatile unsigned long *)WPDACTL)
149#define pWPDA0 ((volatile void **)WPDA0)
150#define pWPDA1 ((volatile void **)WPDA1)
151#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
152#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
153#define pWPSTAT ((volatile unsigned long *)WPSTAT)
154
Aubrey Lif83a65c2007-03-10 23:49:29 +0800[diff] [blame]155/* Performance Monitor Registers */
Wolfgang Denk97caf672006-03-12 02:12:27 +0100[diff] [blame]156#define pPFCTL ((volatile unsigned long *)PFCTL)
157#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
158#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
159
Aubrey.Li9da597f2007-03-09 13:38:44 +0800[diff] [blame]160#endif /* _CDEF_LPBLACKFIN_H */