Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2006 Freescale Semiconductor, Inc. |
| 4 | * |
| 5 | * Dave Liu <daveliu@freescale.com> |
| 6 | * based on source code of Shlomi Gridish |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 7 | */ |
| 8 | |
Masahiro Yamada | adae2ec | 2016-09-21 11:28:53 +0900 | [diff] [blame] | 9 | #include <common.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 10 | #include <linux/errno.h> |
Masahiro Yamada | adae2ec | 2016-09-21 11:28:53 +0900 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/immap_85xx.h> |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 13 | |
Zhao Qiang | b818ba2 | 2014-03-21 16:21:45 +0800 | [diff] [blame] | 14 | #if defined(CONFIG_QE) && !defined(CONFIG_U_QE) |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 15 | #define NUM_OF_PINS 32 |
| 16 | void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) |
| 17 | { |
| 18 | u32 pin_2bit_mask; |
| 19 | u32 pin_2bit_dir; |
| 20 | u32 pin_2bit_assign; |
| 21 | u32 pin_1bit_mask; |
| 22 | u32 tmp_val; |
Tom Rini | d5c3bf2 | 2022-10-28 20:27:12 -0400 | [diff] [blame] | 23 | volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 24 | volatile par_io_t *par_io = (volatile par_io_t *) |
Kumar Gala | ec1340d | 2007-11-27 23:25:02 -0600 | [diff] [blame] | 25 | &(gur->qe_par_io); |
Andy Fleming | ee0e917 | 2007-08-14 00:14:25 -0500 | [diff] [blame] | 26 | |
| 27 | /* Caculate pin location and 2bit mask and dir */ |
| 28 | pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); |
| 29 | pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); |
| 30 | |
| 31 | /* Setup the direction */ |
| 32 | tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ |
| 33 | in_be32(&par_io[port].cpdir2) : |
| 34 | in_be32(&par_io[port].cpdir1); |
| 35 | |
| 36 | if (pin > (NUM_OF_PINS/2) -1) { |
| 37 | out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val); |
| 38 | out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val); |
| 39 | } else { |
| 40 | out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val); |
| 41 | out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); |
| 42 | } |
| 43 | |
| 44 | /* Calculate pin location for 1bit mask */ |
| 45 | pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); |
| 46 | |
| 47 | /* Setup the open drain */ |
| 48 | tmp_val = in_be32(&par_io[port].cpodr); |
| 49 | if (open_drain) |
| 50 | out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val); |
| 51 | else |
| 52 | out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val); |
| 53 | |
| 54 | /* Setup the assignment */ |
| 55 | tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? |
| 56 | in_be32(&par_io[port].cppar2): |
| 57 | in_be32(&par_io[port].cppar1); |
| 58 | pin_2bit_assign = (u32)(assign |
| 59 | << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); |
| 60 | |
| 61 | /* Clear and set 2 bits mask */ |
| 62 | if (pin > (NUM_OF_PINS/2) - 1) { |
| 63 | out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val); |
| 64 | out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val); |
| 65 | } else { |
| 66 | out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val); |
| 67 | out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val); |
| 68 | } |
| 69 | } |
| 70 | |
| 71 | #endif /* CONFIG_QE */ |