| developer | 18ec8d6 | 2020-11-12 16:35:52 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _MT7620_H_ |
| 9 | #define _MT7620_H_ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | |
| 13 | #define SYSCTL_BASE 0x10000000 |
| 14 | #define SYSCTL_SIZE 0x100 |
| 15 | #define MEMCTL_BASE 0x10000300 |
| 16 | #define MEMCTL_SIZE 0x100 |
| 17 | #define UARTFULL_BASE 0x10000500 |
| 18 | #define UARTFULL_SIZE 0x100 |
| 19 | #define UARTLITE_BASE 0x10000c00 |
| 20 | #define UARTLITE_SIZE 0x100 |
| 21 | |
| 22 | #define SYSCTL_CHIP_REV_ID_REG 0x0c |
| 23 | #define PKG_ID BIT(16) |
| 24 | #define PKG_ID_A 1 |
| 25 | #define PKG_ID_N 0 |
| 26 | #define VER_S 8 |
| 27 | #define VER_M GENMASK(11, 8) |
| 28 | #define ECO_S 0 |
| 29 | #define ECO_M GENMASK(3, 0) |
| 30 | |
| 31 | #define SYSCTL_SYSCFG0_REG 0x10 |
| 32 | #define XTAL_FREQ_SEL BIT(6) |
| 33 | #define XTAL_40MHZ 1 |
| 34 | #define XTAL_20MHZ 0 |
| 35 | #define DRAM_TYPE_S 4 |
| 36 | #define DRAM_TYPE_M GENMASK(5, 4) |
| 37 | #define DRAM_SDRAM 3 |
| 38 | #define DRAM_DDR2 2 |
| 39 | #define DRAM_DDR1 1 |
| 40 | #define DRAM_SDRAM_E1 0 |
| 41 | #define CHIP_MODE_S 0 |
| 42 | #define CHIP_MODE_M GENMASK(3, 0) |
| 43 | |
| 44 | #define SYSCTL_SYSCFG1_REG 0x14 |
| 45 | #define GE2_MODE_S 14 |
| 46 | #define GE2_MODE_M GENMASK(15, 14) |
| 47 | #define GE1_MODE_S 12 |
| 48 | #define GE1_MODE_M GENMASK(13, 12) |
| 49 | #define USB0_HOST_MODE BIT(10) |
| 50 | #define PCIE_RC_MODE BIT(8) |
| 51 | #define GE_MODE_M GENMASK(1, 0) |
| 52 | |
| 53 | #define SYSCTL_RSTCTL_REG 0x34 |
| 54 | #define MC_RST BIT(10) |
| 55 | #define SYS_RST BIT(0) |
| 56 | |
| 57 | #define SYSCTL_CLKCFG0_REG 0x2c |
| 58 | #define PERI_CLK_SEL BIT(4) |
| 59 | |
| 60 | #define SYSCTL_CPU_SYS_CLKCFG_REG 0x3c |
| 61 | #define CPU_OCP_RATIO_S 16 |
| 62 | #define CPU_OCP_RATIO_M GENMASK(19, 16) |
| 63 | #define CPU_FDIV_S 8 |
| 64 | #define CPU_FDIV_M GENMASK(12, 8) |
| 65 | #define CPU_FFRAC_S 0 |
| 66 | #define CPU_FFRAC_M GENMASK(4, 0) |
| 67 | |
| 68 | #define SYSCTL_CUR_CLK_STS_REG 0x44 |
| 69 | #define CUR_CPU_OCP_RATIO_S 16 |
| 70 | #define CUR_CPU_OCP_RATIO_M GENMASK(19, 16) |
| 71 | #define CUR_CPU_FDIV_S 8 |
| 72 | #define CUR_CPU_FDIV_M GENMASK(12, 8) |
| 73 | #define CUR_CPU_FFRAC_S 0 |
| 74 | #define CUR_CPU_FFRAC_M GENMASK(4, 0) |
| 75 | |
| 76 | #define SYSCTL_CPLL_CFG0_REG 0x54 |
| 77 | #define CPLL_SW_CFG BIT(31) |
| 78 | #define PLL_MULT_RATIO_S 16 |
| 79 | #define PLL_MULT_RATIO_M GENMASK(18, 16) |
| 80 | #define PLL_DIV_RATIO_S 10 |
| 81 | #define PLL_DIV_RATIO_M GENMASK(11, 10) |
| 82 | #define SSC_UP_BOUND_S 8 |
| 83 | #define SSC_UP_BOUND_M GENMASK(9, 8) |
| 84 | #define SSC_EN BIT(7) |
| 85 | #define SSC_SWING_S 4 |
| 86 | #define SSC_SWING_M GENMASK(6, 4) |
| 87 | |
| 88 | #define SYSCTL_CPLL_CFG1_REG 0x58 |
| 89 | #define CPLL_PD BIT(26) |
| 90 | #define CPU_CLK_AUX1 BIT(25) |
| 91 | #define CPU_CLK_AUX0 BIT(24) |
| 92 | #define CPLL_LD BIT(23) |
| 93 | |
| 94 | #define SYSCTL_GPIOMODE_REG 0x60 |
| 95 | #define UARTL_GPIO_MODE BIT(5) |
| 96 | #define UARTF_SHARE_MODE_S 2 |
| 97 | #define UARTF_SHARE_MODE_M GENMASK(4, 2) |
| 98 | #define UARTF_MODE_UARTF_GPIO 5 |
| 99 | |
| 100 | void mt7620_dram_init(void); |
| 101 | void mt7620_get_clks(u32 *cpu_clk, u32 *sys_clk, u32 *xtal_clk); |
| 102 | |
| 103 | #endif /* _MT7620_H_ */ |