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git01.mediatek.com / filogic / uboot / ae8061433feac532a5c6b6af911197a1e3021f05 / . / drivers / ddr / marvell / a38x / ddr3_init.h
blob: a4c75a9fa68f76d5fbca7f50870a511afa3f6139 [file] [log] [blame]
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]1/*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#ifndef _DDR3_INIT_H
8#define _DDR3_INIT_H
9
10#if defined(CONFIG_ARMADA_38X)
11#include "ddr3_a38x.h"
12#include "ddr3_a38x_mc_static.h"
13#include "ddr3_a38x_topology.h"
14#endif
15#include "ddr3_hws_hw_training.h"
16#include "ddr3_hws_sil_training.h"
17#include "ddr3_logging_def.h"
18#include "ddr3_training_hw_algo.h"
19#include "ddr3_training_ip.h"
20#include "ddr3_training_ip_centralization.h"
21#include "ddr3_training_ip_engine.h"
22#include "ddr3_training_ip_flow.h"
23#include "ddr3_training_ip_pbs.h"
24#include "ddr3_training_ip_prv_if.h"
25#include "ddr3_training_ip_static.h"
26#include "ddr3_training_leveling.h"
27#include "xor.h"
28
29/*
30 * MV_DEBUG_INIT need to be defines, otherwise the output of the
31 * DDR2 training code is not complete and misleading
32 */
33#define MV_DEBUG_INIT
34
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]35#ifdef MV_DEBUG_INIT
36#define DEBUG_INIT_S(s) puts(s)
37#define DEBUG_INIT_D(d, l) printf("%x", d)
38#define DEBUG_INIT_D_10(d, l) printf("%d", d)
39#else
40#define DEBUG_INIT_S(s)
41#define DEBUG_INIT_D(d, l)
42#define DEBUG_INIT_D_10(d, l)
43#endif
44
45#ifdef MV_DEBUG_INIT_FULL
46#define DEBUG_INIT_FULL_S(s) puts(s)
47#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
48#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
49#define DEBUG_WR_REG(reg, val) \
50 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
51 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
52#define DEBUG_RD_REG(reg, val) \
53 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
54 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
55#else
56#define DEBUG_INIT_FULL_S(s)
57#define DEBUG_INIT_FULL_D(d, l)
58#define DEBUG_INIT_FULL_D_10(d, l)
59#define DEBUG_WR_REG(reg, val)
60#define DEBUG_RD_REG(reg, val)
61#endif
62
63#define DEBUG_INIT_FULL_C(s, d, l) \
64 { DEBUG_INIT_FULL_S(s); \
65 DEBUG_INIT_FULL_D(d, l); \
66 DEBUG_INIT_FULL_S("\n"); }
67#define DEBUG_INIT_C(s, d, l) \
68 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
69
70/*
71 * Debug (Enable/Disable modules) and Error report
72 */
73
74#ifdef BASIC_DEBUG
75#define MV_DEBUG_WL
76#define MV_DEBUG_RL
77#define MV_DEBUG_DQS_RESULTS
78#endif
79
80#ifdef FULL_DEBUG
81#define MV_DEBUG_WL
82#define MV_DEBUG_RL
83#define MV_DEBUG_DQS
84
85#define MV_DEBUG_PBS
86#define MV_DEBUG_DFS
87#define MV_DEBUG_MAIN_FULL
88#define MV_DEBUG_DFS_FULL
89#define MV_DEBUG_DQS_FULL
90#define MV_DEBUG_RL_FULL
91#define MV_DEBUG_WL_FULL
92#endif
93
94#if defined(CONFIG_ARMADA_38X)
95#include "ddr3_a38x.h"
96#include "ddr3_a38x_topology.h"
97#endif
98
99/* The following is a list of Marvell status */
100#define MV_ERROR (-1)
101#define MV_OK (0x00) /* Operation succeeded */
102#define MV_FAIL (0x01) /* Operation failed */
103#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
104#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
105#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
106#define MV_BAD_PTR (0x05) /* Illegal pointer value */
107#define MV_BAD_SIZE (0x06) /* Illegal size */
108#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
109#define MV_SET_ERROR (0x08) /* Set operation failed */
110#define MV_GET_ERROR (0x09) /* Get operation failed */
111#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
112#define MV_NOT_FOUND (0x0b) /* Item not found */
113#define MV_NO_MORE (0x0c) /* No more items found */
114#define MV_NO_SUCH (0x0d) /* No such item */
115#define MV_TIMEOUT (0x0e) /* Time Out */
116#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
117#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
118#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
119#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
120#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
121#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
122#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
Vagrant Cascadianedfdb992016-04-30 19:18:00 -0700[diff] [blame]123#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]124#define MV_HW_ERROR (0x17) /* Hardware error */
125#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
126#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
127#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
128#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
129#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
130#define MV_NOT_STARTED (0x1d) /* Not started yet */
131#define MV_BUSY (0x1e) /* Item is busy. */
132#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
133#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
134#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
135#define MV_WRITE_PROTECT (0x22) /* Write protected */
136#define MV_INVALID (int)(-1)
137
138/* For checking function return values */
139#define CHECK_STATUS(orig_func) \
140 { \
141 int status; \
142 status = orig_func; \
143 if (MV_OK != status) \
144 return status; \
145 }
146
147enum log_level {
148 MV_LOG_LEVEL_0,
149 MV_LOG_LEVEL_1,
150 MV_LOG_LEVEL_2,
151 MV_LOG_LEVEL_3
152};
153
154/* Globals */
155extern u8 debug_training;
156extern u8 is_reg_dump;
157extern u8 generic_init_controller;
158extern u32 freq_val[];
159extern u32 is_pll_old;
160extern struct cl_val_per_freq cas_latency_table[];
161extern struct pattern_info pattern_table[];
162extern struct cl_val_per_freq cas_write_latency_table[];
163extern u8 debug_training;
164extern u8 debug_centralization, debug_training_ip, debug_training_bist,
165 debug_pbs, debug_training_static, debug_leveling;
166extern u32 pipe_multicast_mask;
167extern struct hws_tip_config_func_db config_func_info[];
168extern u8 cs_mask_reg[];
169extern u8 twr_mask_table[];
170extern u8 cl_mask_table[];
171extern u8 cwl_mask_table[];
172extern u16 rfc_table[];
173extern u32 speed_bin_table_t_rc[];
174extern u32 speed_bin_table_t_rcd_t_rp[];
175extern u32 ck_delay, ck_delay_16;
176
177extern u32 g_zpri_data;
178extern u32 g_znri_data;
179extern u32 g_zpri_ctrl;
180extern u32 g_znri_ctrl;
181extern u32 g_zpodt_data;
182extern u32 g_znodt_data;
183extern u32 g_zpodt_ctrl;
184extern u32 g_znodt_ctrl;
185extern u32 g_dic;
Chris Packhamae806142018-01-18 17:16:07 +1300[diff] [blame^]186extern u32 g_odt_config_2cs;
187extern u32 g_odt_config_1cs;
Stefan Roese5ffceb82015-03-26 15:36:56 +0100[diff] [blame]188extern u32 g_rtt_nom;
189
190extern u8 debug_training_access;
191extern u8 debug_training_a38x;
192extern u32 first_active_if;
193extern enum hws_ddr_freq init_freq;
194extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
195extern u32 mask_tune_func;
196extern u32 rl_version;
197extern int rl_mid_freq_wa;
198extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
199extern enum hws_ddr_freq medium_freq;
200
201extern u32 ck_delay, ck_delay_16;
202extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
203extern u32 first_active_if;
204extern u32 mask_tune_func;
205extern u32 freq_val[];
206extern enum hws_ddr_freq init_freq;
207extern enum hws_ddr_freq low_freq;
208extern enum hws_ddr_freq medium_freq;
209extern u8 generic_init_controller;
210extern enum auto_tune_stage training_stage;
211extern u32 is_pll_before_init;
212extern u32 is_adll_calib_before_init;
213extern u32 is_dfs_in_init;
214extern int wl_debug_delay;
215extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
216extern u32 p_finger;
217extern u32 n_finger;
218extern u32 freq_val[DDR_FREQ_LIMIT];
219extern u32 start_pattern, end_pattern;
220extern u32 phy_reg0_val;
221extern u32 phy_reg1_val;
222extern u32 phy_reg2_val;
223extern u32 phy_reg3_val;
224extern enum hws_pattern sweep_pattern;
225extern enum hws_pattern pbs_pattern;
226extern u8 is_rzq6;
227extern u32 znri_data_phy_val;
228extern u32 zpri_data_phy_val;
229extern u32 znri_ctrl_phy_val;
230extern u32 zpri_ctrl_phy_val;
231extern u8 debug_training_access;
232extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
233 n_finger_end, p_finger_step, n_finger_step;
234extern u32 mode2_t;
235extern u32 xsb_validate_type;
236extern u32 xsb_validation_base_address;
237extern u32 odt_additional;
238extern u32 debug_mode;
239extern u32 delay_enable;
240extern u32 ca_delay;
241extern u32 debug_dunit;
242extern u32 clamp_tbl[];
243extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
244extern u32 start_pattern, end_pattern;
245
246extern u32 maxt_poll_tries;
247extern u32 is_bist_reset_bit;
248extern u8 debug_training_bist;
249
250extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
251extern u32 debug_mode;
252extern u32 effective_cs;
253extern int ddr3_tip_centr_skip_min_win_check;
254extern u32 *dq_map_table;
255extern enum auto_tune_stage training_stage;
256extern u8 debug_centralization;
257
258extern u32 delay_enable;
259extern u32 start_pattern, end_pattern;
260extern u32 freq_val[DDR_FREQ_LIMIT];
261extern u8 debug_training_hw_alg;
262extern enum auto_tune_stage training_stage;
263
264extern u8 debug_training_ip;
265extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
266extern enum auto_tune_stage training_stage;
267extern u32 effective_cs;
268
269extern u8 debug_leveling;
270extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
271extern enum auto_tune_stage training_stage;
272extern u32 rl_version;
273extern struct cl_val_per_freq cas_latency_table[];
274extern u32 start_xsb_offset;
275extern u32 debug_mode;
276extern u32 odt_config;
277extern u32 effective_cs;
278extern u32 phy_reg1_val;
279
280extern u8 debug_pbs;
281extern u32 effective_cs;
282extern u16 mask_results_dq_reg_map[];
283extern enum hws_ddr_freq medium_freq;
284extern u32 freq_val[];
285extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
286extern enum auto_tune_stage training_stage;
287extern u32 debug_mode;
288extern u32 *dq_map_table;
289
290extern u32 vref;
291extern struct cl_val_per_freq cas_latency_table[];
292extern u32 target_freq;
293extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
294extern u32 clamp_tbl[];
295extern u32 init_freq;
296/* list of allowed frequency listed in order of enum hws_ddr_freq */
297extern u32 freq_val[];
298extern u8 debug_training_static;
299extern u32 first_active_if;
300
301/* Prototypes */
302int ddr3_tip_enable_init_sequence(u32 dev_num);
303
304int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
305
306int ddr3_hws_hw_training(void);
307int ddr3_silicon_pre_init(void);
308int ddr3_silicon_post_init(void);
309int ddr3_post_run_alg(void);
310int ddr3_if_ecc_enabled(void);
311void ddr3_new_tip_ecc_scrub(void);
312
313void ddr3_print_version(void);
314void ddr3_new_tip_dlb_config(void);
315struct hws_topology_map *ddr3_get_topology_map(void);
316
317int ddr3_if_ecc_enabled(void);
318int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
319int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
320int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
321int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
322 struct hws_tip_freq_config_info
323 *freq_config_info);
324int ddr3_a38x_update_topology_map(u32 dev_num,
325 struct hws_topology_map *topology_map);
326int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
327int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
328int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
329 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
330int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
331 u32 if_id, u32 reg_addr, u32 data, u32 mask);
332int ddr3_tip_a38x_get_device_info(u8 dev_num,
333 struct ddr3_device_info *info_ptr);
334
335int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
336
337int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
338int ddr3_tip_restore_dunit_regs(u32 dev_num);
339void print_topology(struct hws_topology_map *topology_db);
340
341u32 mv_board_id_get(void);
342
343int ddr3_load_topology_map(void);
344int ddr3_tip_init_specific_reg_config(u32 dev_num,
345 struct reg_data *reg_config_arr);
346u32 ddr3_tip_get_init_freq(void);
347void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
348int ddr3_tip_tune_training_params(u32 dev_num,
349 struct tune_train_params *params);
350void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
351int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
352void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
353u32 ddr3_get_device_width(u32 cs);
354u32 mv_board_id_index_get(u32 board_id);
355u32 mv_board_id_get(void);
356u32 ddr3_get_bus_width(void);
357void ddr3_set_log_level(u32 n_log_level);
358int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
359
360int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
361
362int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
363int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
364
365int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
366 struct trip_delay_element *table_ptr,
367 int is_wl, u32 *round_trip_delay_arr);
368
369u32 hws_ddr3_tip_max_cs_get(void);
370
371/*
372 * Accessor functions for the registers
373 */
374static inline void reg_write(u32 addr, u32 val)
375{
376 writel(val, INTER_REGS_BASE + addr);
377}
378
379static inline u32 reg_read(u32 addr)
380{
381 return readl(INTER_REGS_BASE + addr);
382}
383
384static inline void reg_bit_set(u32 addr, u32 mask)
385{
386 setbits_le32(INTER_REGS_BASE + addr, mask);
387}
388
389static inline void reg_bit_clr(u32 addr, u32 mask)
390{
391 clrbits_le32(INTER_REGS_BASE + addr, mask);
392}
393
394#endif /* _DDR3_INIT_H */