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Stefan Kristiansson6e560bb2011-11-26 19:04:49 +00001/*
2 * SPR Definitions
3 *
4 * Copyright (C) 2000 Damjan Lampret
5 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
6 * Copyright (C) 2008, 2010 Embecosm Limited
7 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
8 * et al.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This file is part of OpenRISC 1000 Architectural Simulator.
16 */
17
18#ifndef SPR_DEFS__H
19#define SPR_DEFS__H
20
21/* Definition of special-purpose registers (SPRs) */
22
23#define MAX_GRPS (32)
24#define MAX_SPRS_PER_GRP_BITS (11)
25#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
26#define MAX_SPRS (0x10000)
27
28/* Base addresses for the groups */
29#define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS)
30#define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS)
31#define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS)
32#define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS)
33#define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS)
34#define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS)
35#define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS)
36#define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS)
37#define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS)
38#define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS)
39#define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS)
40#define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS)
41
42/* System control and status group */
43#define SPR_VR (SPRGROUP_SYS + 0)
44#define SPR_UPR (SPRGROUP_SYS + 1)
45#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
46#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
47#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
48#define SPR_DCCFGR (SPRGROUP_SYS + 5)
49#define SPR_ICCFGR (SPRGROUP_SYS + 6)
50#define SPR_DCFGR (SPRGROUP_SYS + 7)
51#define SPR_PCCFGR (SPRGROUP_SYS + 8)
52#define SPR_NPC (SPRGROUP_SYS + 16)
53#define SPR_SR (SPRGROUP_SYS + 17)
54#define SPR_PPC (SPRGROUP_SYS + 18)
55#define SPR_FPCSR (SPRGROUP_SYS + 20)
56#define SPR_EPCR_BASE (SPRGROUP_SYS + 32)
57#define SPR_EPCR_LAST (SPRGROUP_SYS + 47)
58#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
59#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
60#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
61#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
62#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
63
64/* Data MMU group */
65#define SPR_DMMUCR (SPRGROUP_DMMU + 0)
66#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
67#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
68#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
69#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
70#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
71
72/* Instruction MMU group */
73#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
74#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
75#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
76#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
77#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
78#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
79
80/* Data cache group */
81#define SPR_DCCR (SPRGROUP_DC + 0)
82#define SPR_DCBPR (SPRGROUP_DC + 1)
83#define SPR_DCBFR (SPRGROUP_DC + 2)
84#define SPR_DCBIR (SPRGROUP_DC + 3)
85#define SPR_DCBWR (SPRGROUP_DC + 4)
86#define SPR_DCBLR (SPRGROUP_DC + 5)
87#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
88#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
89
90/* Instruction cache group */
91#define SPR_ICCR (SPRGROUP_IC + 0)
92#define SPR_ICBPR (SPRGROUP_IC + 1)
93#define SPR_ICBIR (SPRGROUP_IC + 2)
94#define SPR_ICBLR (SPRGROUP_IC + 3)
95#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
96#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
97
98/* MAC group */
99#define SPR_MACLO (SPRGROUP_MAC + 1)
100#define SPR_MACHI (SPRGROUP_MAC + 2)
101
102/* Debug group */
103#define SPR_DVR(N) (SPRGROUP_D + (N))
104#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
105#define SPR_DMR1 (SPRGROUP_D + 16)
106#define SPR_DMR2 (SPRGROUP_D + 17)
107#define SPR_DWCR0 (SPRGROUP_D + 18)
108#define SPR_DWCR1 (SPRGROUP_D + 19)
109#define SPR_DSR (SPRGROUP_D + 20)
110#define SPR_DRR (SPRGROUP_D + 21)
111
112/* Performance counters group */
113#define SPR_PCCR(N) (SPRGROUP_PC + (N))
114#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
115
116/* Power management group */
117#define SPR_PMR (SPRGROUP_PM + 0)
118
119/* PIC group */
120#define SPR_PICMR (SPRGROUP_PIC + 0)
121#define SPR_PICPR (SPRGROUP_PIC + 1)
122#define SPR_PICSR (SPRGROUP_PIC + 2)
123
124/* Tick Timer group */
125#define SPR_TTMR (SPRGROUP_TT + 0)
126#define SPR_TTCR (SPRGROUP_TT + 1)
127
128/*
129 * Bit definitions for the Version Register
130 */
131#define SPR_VR_VER 0xff000000 /* Processor version */
132#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
133#define SPR_VR_RES 0x0000ffc0 /* Reserved */
134#define SPR_VR_REV 0x0000003f /* Processor revision */
135
136#define SPR_VR_VER_OFF 24
137#define SPR_VR_CFG_OFF 16
138#define SPR_VR_REV_OFF 0
139
140/*
141 * Bit definitions for the Unit Present Register
142 */
143#define SPR_UPR_UP 0x00000001 /* UPR present */
144#define SPR_UPR_DCP 0x00000002 /* Data cache present */
145#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
146#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
147#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
148#define SPR_UPR_MP 0x00000020 /* MAC present */
149#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
150#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
151#define SPR_UPR_PMP 0x00000100 /* Power management present */
152#define SPR_UPR_PICP 0x00000200 /* PIC present */
153#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
154#define SPR_UPR_RES 0x00fe0000 /* Reserved */
155#define SPR_UPR_CUP 0xff000000 /* Context units present */
156
157/*
158 * Bit definitions for the CPU configuration register
159 */
160#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
161#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
162#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
163#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
164#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
165#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
166#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
167#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
168
169/*
170 * Bit definitions for the Debug configuration register and other
171 * constants.
172 */
173
174#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
175#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
176#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
177#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
178#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
179#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
180#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
181#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
182#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
183#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
184
185#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
186 2 == n ? SPR_DCFGR_NDP2 : \
187 3 == n ? SPR_DCFGR_NDP3 : \
188 4 == n ? SPR_DCFGR_NDP4 : \
189 5 == n ? SPR_DCFGR_NDP5 : \
190 6 == n ? SPR_DCFGR_NDP6 : \
191 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
192#define MAX_MATCHPOINTS 8
193#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
194
195/*
196 * Bit definitions for the Supervision Register
197 */
198#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
199#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
200#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
201#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
202#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
203#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
204#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
205#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
206#define SPR_SR_CE 0x00000100 /* CID Enable */
207#define SPR_SR_F 0x00000200 /* Condition Flag */
208#define SPR_SR_CY 0x00000400 /* Carry flag */
209#define SPR_SR_OV 0x00000800 /* Overflow flag */
210#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
211#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
212#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
213#define SPR_SR_FO 0x00008000 /* Fixed one */
214#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
215#define SPR_SR_RES 0x0ffe0000 /* Reserved */
216#define SPR_SR_CID 0xf0000000 /* Context ID */
217
218/*
219 * Bit definitions for the Data MMU Control Register
220 */
221#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
222#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
223#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
224#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
225
226/*
227 * Bit definitions for the Instruction MMU Control Register
228 */
229#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
230#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
231#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
232#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
233
234/*
235 * Bit definitions for the Data TLB Match Register
236 */
237#define SPR_DTLBMR_V 0x00000001 /* Valid */
238#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
239#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
240#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
241#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */
242
243/*
244 * Bit definitions for the Data TLB Translate Register
245 */
246#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
247#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
248#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
249#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
250#define SPR_DTLBTR_A 0x00000010 /* Accessed */
251#define SPR_DTLBTR_D 0x00000020 /* Dirty */
252#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
253#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
254#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
255#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
256#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */
257
258/*
259 * Bit definitions for the Instruction TLB Match Register
260 */
261#define SPR_ITLBMR_V 0x00000001 /* Valid */
262#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
263#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
264#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
265#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */
266
267/*
268 * Bit definitions for the Instruction TLB Translate Register
269 */
270#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
271#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
272#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
273#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
274#define SPR_ITLBTR_A 0x00000010 /* Accessed */
275#define SPR_ITLBTR_D 0x00000020 /* Dirty */
276#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
277#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
278#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */
279
280/*
281 * Bit definitions for Data Cache Control register
282 */
283#define SPR_DCCR_EW 0x000000ff /* Enable ways */
284
285/*
286 * Bit definitions for Insn Cache Control register
287 */
288#define SPR_ICCR_EW 0x000000ff /* Enable ways */
289
290/*
291 * Bit definitions for Data Cache Configuration Register
292 */
293
294#define SPR_DCCFGR_NCW 0x00000007
295#define SPR_DCCFGR_NCS 0x00000078
296#define SPR_DCCFGR_CBS 0x00000080
297#define SPR_DCCFGR_CWS 0x00000100
298#define SPR_DCCFGR_CCRI 0x00000200
299#define SPR_DCCFGR_CBIRI 0x00000400
300#define SPR_DCCFGR_CBPRI 0x00000800
301#define SPR_DCCFGR_CBLRI 0x00001000
302#define SPR_DCCFGR_CBFRI 0x00002000
303#define SPR_DCCFGR_CBWBRI 0x00004000
304
305#define SPR_DCCFGR_NCW_OFF 0
306#define SPR_DCCFGR_NCS_OFF 3
307#define SPR_DCCFGR_CBS_OFF 7
308
309/*
310 * Bit definitions for Instruction Cache Configuration Register
311 */
312#define SPR_ICCFGR_NCW 0x00000007
313#define SPR_ICCFGR_NCS 0x00000078
314#define SPR_ICCFGR_CBS 0x00000080
315#define SPR_ICCFGR_CCRI 0x00000200
316#define SPR_ICCFGR_CBIRI 0x00000400
317#define SPR_ICCFGR_CBPRI 0x00000800
318#define SPR_ICCFGR_CBLRI 0x00001000
319
320#define SPR_ICCFGR_NCW_OFF 0
321#define SPR_ICCFGR_NCS_OFF 3
322#define SPR_ICCFGR_CBS_OFF 7
323
324/*
325 * Bit definitions for Data MMU Configuration Register
326 */
327#define SPR_DMMUCFGR_NTW 0x00000003
328#define SPR_DMMUCFGR_NTS 0x0000001C
329#define SPR_DMMUCFGR_NAE 0x000000E0
330#define SPR_DMMUCFGR_CRI 0x00000100
331#define SPR_DMMUCFGR_PRI 0x00000200
332#define SPR_DMMUCFGR_TEIRI 0x00000400
333#define SPR_DMMUCFGR_HTR 0x00000800
334
335#define SPR_DMMUCFGR_NTW_OFF 0
336#define SPR_DMMUCFGR_NTS_OFF 2
337
338/*
339 * Bit definitions for Instruction MMU Configuration Register
340 */
341#define SPR_IMMUCFGR_NTW 0x00000003
342#define SPR_IMMUCFGR_NTS 0x0000001C
343#define SPR_IMMUCFGR_NAE 0x000000E0
344#define SPR_IMMUCFGR_CRI 0x00000100
345#define SPR_IMMUCFGR_PRI 0x00000200
346#define SPR_IMMUCFGR_TEIRI 0x00000400
347#define SPR_IMMUCFGR_HTR 0x00000800
348
349#define SPR_IMMUCFGR_NTW_OFF 0
350#define SPR_IMMUCFGR_NTS_OFF 2
351
352/*
353 * Bit definitions for Debug Control registers
354 */
355#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
356#define SPR_DCR_CC 0x0000000e /* Compare condition */
357#define SPR_DCR_SC 0x00000010 /* Signed compare */
358#define SPR_DCR_CT 0x000000e0 /* Compare to */
359
360/* Bit results with SPR_DCR_CC mask */
361#define SPR_DCR_CC_MASKED 0x00000000
362#define SPR_DCR_CC_EQUAL 0x00000002
363#define SPR_DCR_CC_LESS 0x00000004
364#define SPR_DCR_CC_LESSE 0x00000006
365#define SPR_DCR_CC_GREAT 0x00000008
366#define SPR_DCR_CC_GREATE 0x0000000a
367#define SPR_DCR_CC_NEQUAL 0x0000000c
368
369/* Bit results with SPR_DCR_CT mask */
370#define SPR_DCR_CT_DISABLED 0x00000000
371#define SPR_DCR_CT_IFEA 0x00000020
372#define SPR_DCR_CT_LEA 0x00000040
373#define SPR_DCR_CT_SEA 0x00000060
374#define SPR_DCR_CT_LD 0x00000080
375#define SPR_DCR_CT_SD 0x000000a0
376#define SPR_DCR_CT_LSEA 0x000000c0
377#define SPR_DCR_CT_LSD 0x000000e0
378
379/*
380 * Bit definitions for Debug Mode 1 register
381 */
382#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
383#define SPR_DMR1_CW0_AND 0x00000001
384#define SPR_DMR1_CW0_OR 0x00000002
385#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
386#define SPR_DMR1_CW1_AND 0x00000004
387#define SPR_DMR1_CW1_OR 0x00000008
388#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
389#define SPR_DMR1_CW2_AND 0x00000010
390#define SPR_DMR1_CW2_OR 0x00000020
391#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
392#define SPR_DMR1_CW3_AND 0x00000040
393#define SPR_DMR1_CW3_OR 0x00000080
394#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
395#define SPR_DMR1_CW4_AND 0x00000100
396#define SPR_DMR1_CW4_OR 0x00000200
397#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
398#define SPR_DMR1_CW5_AND 0x00000400
399#define SPR_DMR1_CW5_OR 0x00000800
400#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
401#define SPR_DMR1_CW6_AND 0x00001000
402#define SPR_DMR1_CW6_OR 0x00002000
403#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
404#define SPR_DMR1_CW7_AND 0x00004000
405#define SPR_DMR1_CW7_OR 0x00008000
406#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
407#define SPR_DMR1_CW8_AND 0x00010000
408#define SPR_DMR1_CW8_OR 0x00020000
409#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
410#define SPR_DMR1_CW9_AND 0x00040000
411#define SPR_DMR1_CW9_OR 0x00080000
412#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
413#define SPR_DMR1_RES1 0x00300000 /* Reserved */
414#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
415#define SPR_DMR1_BT 0x00800000 /* Branch trace */
416#define SPR_DMR1_RES2 0xff000000 /* Reserved */
417
418/*
419 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
420 */
421#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
422#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
423#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
424#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
425#define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */
426#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
427#define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */
428#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
429
430/*
431 * Bit definitions for Debug watchpoint counter registers
432 */
433#define SPR_DWCR_COUNT 0x0000ffff /* Count */
434#define SPR_DWCR_MATCH 0xffff0000 /* Match */
435#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
436
437/*
438 * Bit definitions for Debug stop register
439 *
440 */
441#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
442#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
443#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
444#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
445#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
446#define SPR_DSR_AE 0x00000020 /* Alignment exception */
447#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
448#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
449#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
450#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
451#define SPR_DSR_RE 0x00000400 /* Range exception */
452#define SPR_DSR_SCE 0x00000800 /* System call exception */
453#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
454#define SPR_DSR_TE 0x00002000 /* Trap exception */
455
456/*
457 * Bit definitions for Debug reason register
458 */
459#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
460#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
461#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
462#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
463#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
464#define SPR_DRR_AE 0x00000020 /* Alignment exception */
465#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
466#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
467#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
468#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
469#define SPR_DRR_RE 0x00000400 /* Range exception */
470#define SPR_DRR_SCE 0x00000800 /* System call exception */
471#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
472#define SPR_DRR_TE 0x00002000 /* Trap exception */
473
474/*
475 * Bit definitions for Performance counters mode registers
476 */
477#define SPR_PCMR_CP 0x00000001 /* Counter present */
478#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
479#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
480#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
481#define SPR_PCMR_LA 0x00000010 /* Load access event */
482#define SPR_PCMR_SA 0x00000020 /* Store access event */
483#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
484#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
485#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
486#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
487#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
488#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
489#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
490#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
491#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
492#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
493
494/*
495 * Bit definitions for the Power management register
496 */
497#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
498#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
499#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
500#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
501#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
502
503/*
504 * Bit definitions for PICMR
505 */
506#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
507
508/*
509 * Bit definitions for PICPR
510 */
511#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
512
513/*
514 * Bit definitions for PICSR
515 */
516#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
517
518/*
519 * Bit definitions for Tick Timer Control Register
520 */
521#define SPR_TTCR_CNT 0xffffffff /* Count, time period */
522#define SPR_TTMR_TP 0x0fffffff /* Time period */
523#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
524#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
525#define SPR_TTMR_DI 0x00000000 /* Disabled */
526#define SPR_TTMR_RT 0x40000000 /* Restart tick */
527#define SPR_TTMR_SR 0x80000000 /* Single run */
528#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
529#define SPR_TTMR_M 0xc0000000 /* Tick mode */
530
531/*
532 * Bit definitions for the FP Control Status Register
533 */
534#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
535#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
536#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
537#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
538#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
539#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
540#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
541#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
542#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
543#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
544#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
545#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
546 SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
547 SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
548
549#define FPCSR_RM_RN (0<<1)
550#define FPCSR_RM_RZ (1<<1)
551#define FPCSR_RM_RIP (2<<1)
552#define FPCSR_RM_RIN (3<<1)
553
554/*
555 * l.nop constants
556 */
557#define NOP_NOP 0x0000 /* Normal nop instruction */
558#define NOP_EXIT 0x0001 /* End of simulation */
559#define NOP_REPORT 0x0002 /* Simple report */
560#define NOP_PUTC 0x0004 /* Simputc instruction */
561#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */
562#define NOP_GET_TICKS 0x0006 /* Get # ticks running */
563#define NOP_GET_PS 0x0007 /* Get picosecs/cycle */
564#define NOP_REPORT_FIRST 0x0400 /* Report with number */
565#define NOP_REPORT_LAST 0x03ff /* Report with number */
566
567#endif /* SPR_DEFS__H */