blob: aee1849a71f674745cb8e55ed72beb1ecb364d71 [file] [log] [blame]
Bruce Suen6fbb4262024-03-11 21:43:14 -04001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Author:
4 * Felix Matouschek <felix@matouschek.org>
5 */
6
7#include <linux/bitfield.h>
8#ifndef __UBOOT__
9#include <linux/device.h>
10#include <linux/kernel.h>
11#endif
12#include <linux/mtd/spinand.h>
13
14#define SPINAND_MFR_XTX 0x0B
15
16#define XT26G0XA_STATUS_ECC_MASK GENMASK(5, 2)
17#define XT26G0XA_STATUS_ECC_NO_DETECTED (0 << 2)
18#define XT26G0XA_STATUS_ECC_8_CORRECTED (3 << 4)
19#define XT26G0XA_STATUS_ECC_UNCOR_ERROR (2 << 4)
20
21#define XT26XXXD_STATUS_ECC3_ECC2_MASK GENMASK(7, 6)
22#define XT26XXXD_STATUS_ECC_NO_DETECTED (0)
23#define XT26XXXD_STATUS_ECC_1_7_CORRECTED (1)
24#define XT26XXXD_STATUS_ECC_8_CORRECTED (3)
25#define XT26XXXD_STATUS_ECC_UNCOR_ERROR (2)
26
27static SPINAND_OP_VARIANTS(read_cache_variants,
28 SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
29 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
30 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
31 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
32 SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
33 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
34
35static SPINAND_OP_VARIANTS(write_cache_variants,
36 SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
37 SPINAND_PROG_LOAD(true, 0, NULL, 0));
38
39static SPINAND_OP_VARIANTS(update_cache_variants,
40 SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
41 SPINAND_PROG_LOAD(false, 0, NULL, 0));
42
43static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
44 struct mtd_oob_region *region)
45{
46 if (section)
47 return -ERANGE;
48
49 region->offset = 48;
50 region->length = 16;
51
52 return 0;
53}
54
55static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
56 struct mtd_oob_region *region)
57{
58 if (section)
59 return -ERANGE;
60
61 region->offset = 1;
62 region->length = 47;
63
64 return 0;
65}
66
67static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {
68 .ecc = xt26g0xa_ooblayout_ecc,
69 .rfree = xt26g0xa_ooblayout_free,
70};
71
72static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
73 u8 status)
74{
75 status = status & XT26G0XA_STATUS_ECC_MASK;
76
77 switch (status) {
78 case XT26G0XA_STATUS_ECC_NO_DETECTED:
79 return 0;
80 case XT26G0XA_STATUS_ECC_8_CORRECTED:
81 return 8;
82 case XT26G0XA_STATUS_ECC_UNCOR_ERROR:
83 return -EBADMSG;
84 default:
85 break;
86 }
87
88 /* At this point values greater than (2 << 4) are invalid */
89 if (status > XT26G0XA_STATUS_ECC_UNCOR_ERROR)
90 return -EINVAL;
91
92 /* (1 << 2) through (7 << 2) are 1-7 corrected errors */
93 return status >> 2;
94}
95
96static int xt26xxxd_ooblayout_ecc(struct mtd_info *mtd, int section,
97 struct mtd_oob_region *region)
98{
99 if (section)
100 return -ERANGE;
101
102 region->offset = mtd->oobsize / 2;
103 region->length = mtd->oobsize / 2;
104
105 return 0;
106}
107
108static int xt26xxxd_ooblayout_free(struct mtd_info *mtd, int section,
109 struct mtd_oob_region *region)
110{
111 if (section)
112 return -ERANGE;
113
114 region->offset = 2;
115 region->length = mtd->oobsize / 2 - 2;
116
117 return 0;
118}
119
120static const struct mtd_ooblayout_ops xt26xxxd_ooblayout = {
121 .ecc = xt26xxxd_ooblayout_ecc,
122 .rfree = xt26xxxd_ooblayout_free,
123};
124
125static int xt26xxxd_ecc_get_status(struct spinand_device *spinand,
126 u8 status)
127{
128 switch (FIELD_GET(STATUS_ECC_MASK, status)) {
129 case XT26XXXD_STATUS_ECC_NO_DETECTED:
130 return 0;
131 case XT26XXXD_STATUS_ECC_UNCOR_ERROR:
132 return -EBADMSG;
133 case XT26XXXD_STATUS_ECC_1_7_CORRECTED:
134 return 4 + FIELD_GET(XT26XXXD_STATUS_ECC3_ECC2_MASK, status);
135 case XT26XXXD_STATUS_ECC_8_CORRECTED:
136 return 8;
137 default:
138 break;
139 }
140
141 return -EINVAL;
142}
143
144static const struct spinand_info xtx_spinand_table[] = {
145 SPINAND_INFO("XT26G01A",
146 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),
147 NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
148 NAND_ECCREQ(8, 512),
149 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
150 &write_cache_variants,
151 &update_cache_variants),
152 SPINAND_HAS_QE_BIT,
153 SPINAND_ECCINFO(&xt26g0xa_ooblayout,
154 xt26g0xa_ecc_get_status)),
155 SPINAND_INFO("XT26G02A",
156 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2),
157 NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
158 NAND_ECCREQ(8, 512),
159 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
160 &write_cache_variants,
161 &update_cache_variants),
162 SPINAND_HAS_QE_BIT,
163 SPINAND_ECCINFO(&xt26g0xa_ooblayout,
164 xt26g0xa_ecc_get_status)),
165 SPINAND_INFO("XT26G04A",
166 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3),
167 NAND_MEMORG(1, 2048, 64, 128, 2048, 40, 1, 1, 1),
168 NAND_ECCREQ(8, 512),
169 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
170 &write_cache_variants,
171 &update_cache_variants),
172 SPINAND_HAS_QE_BIT,
173 SPINAND_ECCINFO(&xt26g0xa_ooblayout,
174 xt26g0xa_ecc_get_status)),
175 SPINAND_INFO("XT26G01D",
176 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x31),
177 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
178 NAND_ECCREQ(8, 512),
179 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
180 &write_cache_variants,
181 &update_cache_variants),
182 0,
183 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
184 xt26xxxd_ecc_get_status)),
185 SPINAND_INFO("XT26G11D",
186 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x34),
187 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
188 NAND_ECCREQ(8, 512),
189 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
190 &write_cache_variants,
191 &update_cache_variants),
192 0,
193 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
194 xt26xxxd_ecc_get_status)),
195 SPINAND_INFO("XT26Q01D",
196 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x51),
197 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
198 NAND_ECCREQ(8, 512),
199 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
200 &write_cache_variants,
201 &update_cache_variants),
202 0,
203 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
204 xt26xxxd_ecc_get_status)),
205 SPINAND_INFO("XT26G02D",
206 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x32),
207 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
208 NAND_ECCREQ(8, 512),
209 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
210 &write_cache_variants,
211 &update_cache_variants),
212 0,
213 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
214 xt26xxxd_ecc_get_status)),
215 SPINAND_INFO("XT26G12D",
216 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x35),
217 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
218 NAND_ECCREQ(8, 512),
219 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
220 &write_cache_variants,
221 &update_cache_variants),
222 0,
223 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
224 xt26xxxd_ecc_get_status)),
225 SPINAND_INFO("XT26Q02D",
226 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
227 NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
228 NAND_ECCREQ(8, 512),
229 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
230 &write_cache_variants,
231 &update_cache_variants),
232 0,
233 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
234 xt26xxxd_ecc_get_status)),
235 SPINAND_INFO("XT26G04D",
236 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x33),
237 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
238 NAND_ECCREQ(8, 512),
239 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
240 &write_cache_variants,
241 &update_cache_variants),
242 0,
243 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
244 xt26xxxd_ecc_get_status)),
245 SPINAND_INFO("XT26Q04D",
246 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x53),
247 NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
248 NAND_ECCREQ(8, 512),
249 SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
250 &write_cache_variants,
251 &update_cache_variants),
252 0,
253 SPINAND_ECCINFO(&xt26xxxd_ooblayout,
254 xt26xxxd_ecc_get_status)),
255};
256
257static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {
258};
259
260const struct spinand_manufacturer xtx_spinand_manufacturer = {
261 .id = SPINAND_MFR_XTX,
262 .name = "XTX",
263 .chips = xtx_spinand_table,
264 .nchips = ARRAY_SIZE(xtx_spinand_table),
265 .ops = &xtx_spinand_manuf_ops,
266};