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Prabhakar Kushwaha5350b992015-03-19 09:20:46 -07001/*
Yogesh Gaur318c32f2017-11-15 11:59:31 +05302 * Copyright (C) 2014-2016 Freescale Semiconductor
3 * Copyright 2017 NXP
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -07004 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __LDPAA_ETH_H
9#define __LDPAA_ETH_H
10
11#include <linux/netdevice.h>
12#include <fsl-mc/fsl_mc.h>
13#include <fsl-mc/fsl_dpaa_fd.h>
14#include <fsl-mc/fsl_dprc.h>
15#include <fsl-mc/fsl_dpni.h>
16#include <fsl-mc/fsl_dpbp.h>
17#include <fsl-mc/fsl_dpio.h>
18#include <fsl-mc/fsl_qbman_portal.h>
19#include <fsl-mc/fsl_mc_private.h>
20
21
22enum ldpaa_eth_type {
23 LDPAA_ETH_1G_E,
24 LDPAA_ETH_10G_E,
25};
26
27/* Arbitrary values for now, but we'll need to tune */
Prabhakar Kushwaha0c999772015-12-24 15:33:25 +053028#define LDPAA_ETH_NUM_BUFS (7 * 7)
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -070029#define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2)
30#define LDPAA_ETH_RX_BUFFER_SIZE 2048
31
Prabhakar Kushwaha9a934802015-11-04 12:26:02 +053032/* Hardware requires alignment for buffer address and length: 256-byte
33 * for ingress, 64-byte for egress. Using 256 for both.
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -070034 */
Prabhakar Kushwaha9a934802015-11-04 12:26:02 +053035#define LDPAA_ETH_BUF_ALIGN 256
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -070036
37/* So far we're only accomodating a skb backpointer in the frame's
38 * software annotation, but the hardware options are either 0 or 64.
39 */
40#define LDPAA_ETH_SWA_SIZE 64
41
42/* Annotation valid bits in FD FRC */
43#define LDPAA_FD_FRC_FASV 0x8000
44#define LDPAA_FD_FRC_FAEADV 0x4000
45#define LDPAA_FD_FRC_FAPRV 0x2000
46#define LDPAA_FD_FRC_FAIADV 0x1000
47#define LDPAA_FD_FRC_FASWOV 0x0800
48#define LDPAA_FD_FRC_FAICFDV 0x0400
49
50/* Annotation bits in FD CTRL */
51#define LDPAA_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
52#define LDPAA_FD_CTRL_PTA 0x00800000
53#define LDPAA_FD_CTRL_PTV1 0x00400000
54
55/* TODO: we may want to move this and other WRIOP related defines
56 * to a separate header
57 */
58/* Frame annotation status */
59struct ldpaa_fas {
60 u8 reserved;
61 u8 ppid;
62 __le16 ifpid;
63 __le32 status;
64} __packed;
65
66/* Debug frame, otherwise supposed to be discarded */
67#define LDPAA_ETH_FAS_DISC 0x80000000
68/* MACSEC frame */
69#define LDPAA_ETH_FAS_MS 0x40000000
70#define LDPAA_ETH_FAS_PTP 0x08000000
71/* Ethernet multicast frame */
72#define LDPAA_ETH_FAS_MC 0x04000000
73/* Ethernet broadcast frame */
74#define LDPAA_ETH_FAS_BC 0x02000000
75#define LDPAA_ETH_FAS_KSE 0x00040000
76#define LDPAA_ETH_FAS_EOFHE 0x00020000
77#define LDPAA_ETH_FAS_MNLE 0x00010000
78#define LDPAA_ETH_FAS_TIDE 0x00008000
79#define LDPAA_ETH_FAS_PIEE 0x00004000
80/* Frame length error */
81#define LDPAA_ETH_FAS_FLE 0x00002000
82/* Frame physical error; our favourite pastime */
83#define LDPAA_ETH_FAS_FPE 0x00001000
84#define LDPAA_ETH_FAS_PTE 0x00000080
85#define LDPAA_ETH_FAS_ISP 0x00000040
86#define LDPAA_ETH_FAS_PHE 0x00000020
87#define LDPAA_ETH_FAS_BLE 0x00000010
88/* L3 csum validation performed */
89#define LDPAA_ETH_FAS_L3CV 0x00000008
90/* L3 csum error */
91#define LDPAA_ETH_FAS_L3CE 0x00000004
92/* L4 csum validation performed */
93#define LDPAA_ETH_FAS_L4CV 0x00000002
94/* L4 csum error */
95#define LDPAA_ETH_FAS_L4CE 0x00000001
96/* These bits always signal errors */
97#define LDPAA_ETH_RX_ERR_MASK (LDPAA_ETH_FAS_DISC | \
98 LDPAA_ETH_FAS_KSE | \
99 LDPAA_ETH_FAS_EOFHE | \
100 LDPAA_ETH_FAS_MNLE | \
101 LDPAA_ETH_FAS_TIDE | \
102 LDPAA_ETH_FAS_PIEE | \
103 LDPAA_ETH_FAS_FLE | \
104 LDPAA_ETH_FAS_FPE | \
105 LDPAA_ETH_FAS_PTE | \
106 LDPAA_ETH_FAS_ISP | \
107 LDPAA_ETH_FAS_PHE | \
108 LDPAA_ETH_FAS_BLE | \
109 LDPAA_ETH_FAS_L3CE | \
110 LDPAA_ETH_FAS_L4CE)
111/* Unsupported features in the ingress */
112#define LDPAA_ETH_RX_UNSUPP_MASK LDPAA_ETH_FAS_MS
113/* TODO trim down the bitmask; not all of them apply to Tx-confirm */
114#define LDPAA_ETH_TXCONF_ERR_MASK (LDPAA_ETH_FAS_KSE | \
115 LDPAA_ETH_FAS_EOFHE | \
116 LDPAA_ETH_FAS_MNLE | \
117 LDPAA_ETH_FAS_TIDE)
118
119struct ldpaa_eth_priv {
120 struct eth_device *net_dev;
Yogesh Gaur318c32f2017-11-15 11:59:31 +0530121 uint32_t dpmac_id;
Prabhakar Kushwaha52d2e2c2015-11-04 12:26:00 +0530122 uint16_t dpmac_handle;
123
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700124 uint16_t tx_data_offset;
125
126 uint32_t rx_dflt_fqid;
127 uint16_t tx_qdid;
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700128 uint16_t tx_flow_id;
129
130 enum ldpaa_eth_type type; /* 1G or 10G ethernet */
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700131 struct phy_device *phydev;
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700132};
133
Prabhakar Kushwaha52d2e2c2015-11-04 12:26:00 +0530134struct dprc_endpoint dpmac_endpoint;
135struct dprc_endpoint dpni_endpoint;
136
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700137extern struct fsl_mc_io *dflt_mc_io;
138extern struct fsl_dpbp_obj *dflt_dpbp;
139extern struct fsl_dpio_obj *dflt_dpio;
Prabhakar Kushwaha52d2e2c2015-11-04 12:26:00 +0530140extern struct fsl_dpni_obj *dflt_dpni;
141extern uint16_t dflt_dprc_handle;
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700142
143static void ldpaa_dpbp_drain_cnt(int count);
144static void ldpaa_dpbp_drain(void);
145static int ldpaa_dpbp_seed(uint16_t bpid);
146static void ldpaa_dpbp_free(void);
147static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv);
148static int ldpaa_dpbp_setup(void);
149static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv);
Prabhakar Kushwaha52d2e2c2015-11-04 12:26:00 +0530150static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv);
151static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv);
Prabhakar Kushwaha5350b992015-03-19 09:20:46 -0700152#endif /* __LDPAA_H */