| Peter Tyser | 1c2b329 | 2008-12-17 16:36:23 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Extreme Engineering Solutions, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <asm/fsl_ddr_sdram.h> |
| 25 | #include <asm/mmu.h> |
| 26 | |
| 27 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 28 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 29 | #endif |
| 30 | |
| 31 | phys_size_t initdram(int board_type) |
| 32 | { |
| 33 | phys_size_t dram_size = fsl_ddr_sdram(); |
| 34 | |
| 35 | dram_size = setup_ddr_tlbs(dram_size / 0x100000); |
| 36 | |
| 37 | dram_size *= 0x100000; |
| 38 | |
| 39 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 40 | /* Initialize and enable DDR ECC */ |
| 41 | ddr_enable_ecc(dram_size); |
| 42 | #endif |
| 43 | |
| 44 | return dram_size; |
| 45 | } |
| 46 | |
| 47 | #if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1) |
| 48 | void board_add_ram_info(int use_default) |
| 49 | { |
| 50 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) |
| 51 | volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); |
| 52 | #endif |
| 53 | |
| 54 | puts(" ("); |
| 55 | |
| 56 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) |
| 57 | /* Print interleaving information */ |
| 58 | if (ddr1->cs0_config & 0x20000000) { |
| 59 | switch ((ddr1->cs0_config >> 24) & 0xf) { |
| 60 | case 0: |
| 61 | puts("cache line"); |
| 62 | break; |
| 63 | case 1: |
| 64 | puts("page"); |
| 65 | break; |
| 66 | case 2: |
| 67 | puts("bank"); |
| 68 | break; |
| 69 | case 3: |
| 70 | puts("super-bank"); |
| 71 | break; |
| 72 | default: |
| 73 | puts("invalid"); |
| 74 | break; |
| 75 | } |
| 76 | } else { |
| 77 | puts("no"); |
| 78 | } |
| 79 | |
| 80 | puts(" interleaving"); |
| 81 | #endif |
| 82 | |
| 83 | #if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC) |
| 84 | puts(", "); |
| 85 | #endif |
| 86 | |
| 87 | #if defined(CONFIG_DDR_ECC) |
| 88 | puts("ECC enabled"); |
| 89 | #endif |
| 90 | |
| 91 | puts(")"); |
| 92 | } |
| 93 | #endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */ |