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git01.mediatek.com / filogic / uboot / ae022cf373bd1d205e776fcd5b4bc7ccdc739fe3 / . / arch / arm / dts / k3-j721s2-som-p0.dtsi
blob: c0687fece017546fd112edc1cfb841fcdb46a2a0 [file] [log] [blame]
Aswath Govindraju20973c32022-01-25 20:56:41 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j721s2.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 memory@80000000 {
13 device_type = "memory";
14 /* 16 GB RAM */
15 reg = <0x00 0x80000000 0x00 0x80000000>,
16 <0x08 0x80000000 0x03 0x80000000>;
17 };
18
19 reserved_memory: reserved-memory {
20 #address-cells = <2>;
21 #size-cells = <2>;
22 ranges;
23
24 secure_ddr: optee@9e800000 {
25 reg = <0x00 0x9e800000 0x00 0x01800000>;
26 alignment = <0x1000>;
27 no-map;
28 };
29
30 };
31
32 transceiver0: can-phy0 {
33 /* standby pin has been grounded by default */
34 compatible = "ti,tcan1042";
35 #phy-cells = <0>;
36 max-bitrate = <5000000>;
37 };
38};
39
40&main_pmx0 {
41 main_i2c0_pins_default: main-i2c0-pins-default {
42 pinctrl-single,pins = <
43 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
44 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
45 >;
46 };
47
48 main_mcan16_pins_default: main-mcan16-pins-default {
49 pinctrl-single,pins = <
50 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
51 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
52 >;
53 };
54};
55
56&main_i2c0 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&main_i2c0_pins_default>;
59 clock-frequency = <400000>;
60
61 exp_som: gpio@21 {
62 compatible = "ti,tca6408";
63 reg = <0x21>;
64 gpio-controller;
65 #gpio-cells = <2>;
66 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
67 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
68 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
69 "GPIO_LIN_EN", "CAN_STB";
70 };
71};
72
73&main_mcan16 {
74 pinctrl-0 = <&main_mcan16_pins_default>;
75 pinctrl-names = "default";
76 phys = <&transceiver0>;
77};
78
79&mailbox0_cluster0 {
80 status = "disabled";
81};
82
83&mailbox0_cluster1 {
84 status = "disabled";
85};
86
87&mailbox0_cluster2 {
88 status = "disabled";
89};
90
91&mailbox0_cluster3 {
92 status = "disabled";
93};
94
95&mailbox0_cluster4 {
96 status = "disabled";
97};
98
99&mailbox0_cluster5 {
100 status = "disabled";
101};
102
103&mailbox0_cluster6 {
104 status = "disabled";
105};
106
107&mailbox0_cluster7 {
108 status = "disabled";
109};
110
111&mailbox0_cluster8 {
112 status = "disabled";
113};
114
115&mailbox0_cluster9 {
116 status = "disabled";
117};
118
119&mailbox0_cluster10 {
120 status = "disabled";
121};
122
123&mailbox0_cluster11 {
124 status = "disabled";
125};
126
127&mailbox1_cluster0 {
128 status = "disabled";
129};
130
131&mailbox1_cluster1 {
132 status = "disabled";
133};
134
135&mailbox1_cluster2 {
136 status = "disabled";
137};
138
139&mailbox1_cluster3 {
140 status = "disabled";
141};
142
143&mailbox1_cluster4 {
144 status = "disabled";
145};
146
147&mailbox1_cluster5 {
148 status = "disabled";
149};
150
151&mailbox1_cluster6 {
152 status = "disabled";
153};
154
155&mailbox1_cluster7 {
156 status = "disabled";
157};
158
159&mailbox1_cluster8 {
160 status = "disabled";
161};
162
163&mailbox1_cluster9 {
164 status = "disabled";
165};
166
167&mailbox1_cluster10 {
168 status = "disabled";
169};
170
171&mailbox1_cluster11 {
172 status = "disabled";
173};