Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Sifive, Inc. |
| 4 | * Author: Sagar Kadam <sagar.kadam@sifive.com> |
| 5 | */ |
| 6 | |
Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 7 | #include <dm.h> |
| 8 | #include <reset-uclass.h> |
| 9 | #include <asm/io.h> |
| 10 | #include <dm/device_compat.h> |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 11 | #include <dm/device-internal.h> |
Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 12 | #include <dm/lists.h> |
| 13 | #include <linux/bitops.h> |
| 14 | |
| 15 | #define PRCI_RESETREG_OFFSET 0x28 |
| 16 | |
| 17 | struct sifive_reset_priv { |
| 18 | void *base; |
| 19 | /* number of reset signals */ |
| 20 | int nr_reset; |
| 21 | }; |
| 22 | |
| 23 | static int sifive_rst_trigger(struct reset_ctl *rst, bool level) |
| 24 | { |
| 25 | struct sifive_reset_priv *priv = dev_get_priv(rst->dev); |
| 26 | int id = rst->id; |
| 27 | int regval = readl(priv->base + PRCI_RESETREG_OFFSET); |
| 28 | |
| 29 | /* Derive bitposition from rst id */ |
| 30 | if (level) |
| 31 | /* Reset deassert */ |
| 32 | regval |= BIT(id); |
| 33 | else |
| 34 | /* Reset assert */ |
| 35 | regval &= ~BIT(id); |
| 36 | |
| 37 | writel(regval, priv->base + PRCI_RESETREG_OFFSET); |
| 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | static int sifive_reset_assert(struct reset_ctl *rst) |
| 43 | { |
| 44 | return sifive_rst_trigger(rst, false); |
| 45 | } |
| 46 | |
| 47 | static int sifive_reset_deassert(struct reset_ctl *rst) |
| 48 | { |
| 49 | return sifive_rst_trigger(rst, true); |
| 50 | } |
| 51 | |
| 52 | static int sifive_reset_request(struct reset_ctl *rst) |
| 53 | { |
| 54 | struct sifive_reset_priv *priv = dev_get_priv(rst->dev); |
| 55 | |
| 56 | debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__, |
| 57 | rst, rst->dev, rst->id, priv->nr_reset); |
| 58 | |
| 59 | if (rst->id > priv->nr_reset) |
| 60 | return -EINVAL; |
| 61 | |
| 62 | return 0; |
| 63 | } |
| 64 | |
Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 65 | static int sifive_reset_probe(struct udevice *dev) |
| 66 | { |
| 67 | struct sifive_reset_priv *priv = dev_get_priv(dev); |
| 68 | |
| 69 | priv->base = dev_remap_addr(dev); |
| 70 | if (!priv->base) |
| 71 | return -ENOMEM; |
| 72 | |
| 73 | return 0; |
| 74 | } |
| 75 | |
| 76 | int sifive_reset_bind(struct udevice *dev, ulong count) |
| 77 | { |
| 78 | struct udevice *rst_dev; |
| 79 | struct sifive_reset_priv *priv; |
| 80 | int ret; |
| 81 | |
| 82 | ret = device_bind_driver_to_node(dev, "sifive-reset", "reset", |
| 83 | dev_ofnode(dev), &rst_dev); |
| 84 | if (ret) { |
| 85 | dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret); |
| 86 | return ret; |
| 87 | } |
| 88 | priv = malloc(sizeof(struct sifive_reset_priv)); |
| 89 | priv->nr_reset = count; |
Simon Glass | 9558862 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 90 | dev_set_priv(rst_dev, priv); |
Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | const struct reset_ops sifive_reset_ops = { |
| 96 | .request = sifive_reset_request, |
Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 97 | .rst_assert = sifive_reset_assert, |
| 98 | .rst_deassert = sifive_reset_deassert, |
| 99 | }; |
| 100 | |
| 101 | U_BOOT_DRIVER(sifive_reset) = { |
| 102 | .name = "sifive-reset", |
| 103 | .id = UCLASS_RESET, |
| 104 | .ops = &sifive_reset_ops, |
| 105 | .probe = sifive_reset_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 106 | .priv_auto = sizeof(struct sifive_reset_priv), |
Sagar Shrikant Kadam | e1ff6eb | 2020-07-29 02:36:13 -0700 | [diff] [blame] | 107 | }; |