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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jason Cooper8d038fa2011-10-03 13:49:53 +05302/*
Tony Dinh179dd642022-01-30 15:02:30 -08003 * Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com>
4 * Copyright (C) 2011 Jason Cooper <u-boot@lakedaemon.net>
Jason Cooper8d038fa2011-10-03 13:49:53 +05305 *
6 * Based on work by:
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Siddarth Gore <gores@marvell.com>
Jason Cooper8d038fa2011-10-03 13:49:53 +05309 */
10
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Tony Dinh179dd642022-01-30 15:02:30 -080012#include <netdev.h>
Anatolij Gustschincc942142011-10-29 11:19:47 +000013#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +020014#include <asm/arch/soc.h>
Jason Cooper8d038fa2011-10-03 13:49:53 +053015#include <asm/arch/mpp.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Jason Cooper8d038fa2011-10-03 13:49:53 +053017
18DECLARE_GLOBAL_DATA_PTR;
19
Tony Dinh179dd642022-01-30 15:02:30 -080020#define DREAMPLUG_OE_LOW (~(0))
21#define DREAMPLUG_OE_HIGH (~(0))
22#define DREAMPLUG_OE_VAL_LOW 0
23#define DREAMPLUG_OE_VAL_HIGH (0xf << 16) /* 4 LED Pins high */
24
Jason Cooper8d038fa2011-10-03 13:49:53 +053025int board_early_init_f(void)
26{
27 /*
28 * default gpio configuration
29 * There are maximum 64 gpios controlled through 2 sets of registers
30 * the below configuration configures mainly initial LED status
31 */
Stefan Roesec50ab392014-10-22 12:13:11 +020032 mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
33 DREAMPLUG_OE_VAL_HIGH,
34 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
Jason Cooper8d038fa2011-10-03 13:49:53 +053035
36 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +000037 static const u32 kwmpp_config[] = {
Jason Cooper8d038fa2011-10-03 13:49:53 +053038 MPP0_SPI_SCn, /* SPI Flash */
39 MPP1_SPI_MOSI,
40 MPP2_SPI_SCK,
41 MPP3_SPI_MISO,
42 MPP4_NF_IO6,
43 MPP5_NF_IO7,
44 MPP6_SYSRST_OUTn,
45 MPP7_GPO,
46 MPP8_TW_SDA,
47 MPP9_TW_SCK,
48 MPP10_UART0_TXD, /* Serial */
49 MPP11_UART0_RXD,
50 MPP12_SD_CLK, /* SDIO Slot */
51 MPP13_SD_CMD,
52 MPP14_SD_D0,
53 MPP15_SD_D1,
54 MPP16_SD_D2,
55 MPP17_SD_D3,
56 MPP18_NF_IO0,
57 MPP19_NF_IO1,
58 MPP20_GE1_0, /* Gigabit Ethernet */
59 MPP21_GE1_1,
60 MPP22_GE1_2,
61 MPP23_GE1_3,
62 MPP24_GE1_4,
63 MPP25_GE1_5,
64 MPP26_GE1_6,
65 MPP27_GE1_7,
66 MPP28_GE1_8,
67 MPP29_GE1_9,
68 MPP30_GE1_10,
69 MPP31_GE1_11,
70 MPP32_GE1_12,
71 MPP33_GE1_13,
72 MPP34_GE1_14,
73 MPP35_GE1_15,
74 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
75 MPP37_GPIO,
76 MPP38_GPIO,
77 MPP39_GPIO,
78 MPP40_TDM_SPI_SCK,
79 MPP41_TDM_SPI_MISO,
80 MPP42_TDM_SPI_MOSI,
81 MPP43_GPIO,
82 MPP44_GPIO,
83 MPP45_GPIO,
84 MPP46_GPIO,
85 MPP47_GPIO, /* Bluetooth LED */
86 MPP48_GPIO, /* Wifi LED */
87 MPP49_GPIO, /* Wifi AP LED */
88 0
89 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +000090 kirkwood_mpp_conf(kwmpp_config, NULL);
Jason Cooper8d038fa2011-10-03 13:49:53 +053091 return 0;
92}
93
Tony Dinh179dd642022-01-30 15:02:30 -080094int board_eth_init(struct bd_info *bis)
Jason Cooper8d038fa2011-10-03 13:49:53 +053095{
Tony Dinh179dd642022-01-30 15:02:30 -080096 return cpu_eth_init(bis);
Jason Cooper8d038fa2011-10-03 13:49:53 +053097}
98
Tony Dinh179dd642022-01-30 15:02:30 -080099int board_init(void)
Jason Cooper8d038fa2011-10-03 13:49:53 +0530100{
Tony Dinh179dd642022-01-30 15:02:30 -0800101 /* address of boot parameters */
102 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
Tony Dinh4cd94772021-07-25 23:01:19 -0700103
Tony Dinh179dd642022-01-30 15:02:30 -0800104 return 0;
Jason Cooper8d038fa2011-10-03 13:49:53 +0530105}