blob: 587cbb00e7fc02294066a12c2b4288f62e846f14 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roesec50ab392014-10-22 12:13:11 +02002/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Stefan Roesec50ab392014-10-22 12:13:11 +02006 */
7
Stefan Roesec50ab392014-10-22 12:13:11 +02008#include <asm/io.h>
9#include <asm/arch/cpu.h>
10#include <asm/arch/soc.h>
11
12/*
13 * mvebu_config_gpio - GPIO configuration
14 */
15void mvebu_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val,
16 u32 gpp0_oe, u32 gpp1_oe)
17{
18 struct kwgpio_registers *gpio0reg =
19 (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
20 struct kwgpio_registers *gpio1reg =
21 (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
22
23 /* Init GPIOS to default values as per board requirement */
24 writel(gpp0_oe_val, &gpio0reg->dout);
25 writel(gpp1_oe_val, &gpio1reg->dout);
26 writel(gpp0_oe, &gpio0reg->oe);
27 writel(gpp1_oe, &gpio1reg->oe);
28}