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git01.mediatek.com / filogic / uboot / adda11160346c765b10c71c9d71e465a4185ff50 / . / arch / arm / dts / at91-sama5d27_giantboard.dts
blob: 767766d4f81e5d91797a88180b4b2b49ec0bccbd [file] [log] [blame]
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board
4 *
5 * Copyright (C) 2020 Greg Gallagher <greg@embeddedgreg.com>
6 *
7 * Derived from at91-sama5d27_som1_ek.dts
8 *
9 * Copyright (C) 2017 Microchip Corporation
10 * Wenyou Yang <wenyou.yang@microchip.com>
11 */
12/dts-v1/;
13#include "sama5d2.dtsi"
14#include "sama5d2-pinfunc.h"
15
16/ {
17 model = "Giant Board";
18 compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2", "atmel,sama5";
19
20 memory {
21 reg = <0x20000000 0x8000000>;
22 };
23
24 chosen {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]25 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]26 stdout-path = &uart1;
27 };
28
29 ahb {
30 sdmmc1: sdio-host@b0000000 {
31 bus-width = <4>;
32 pinctrl-names = "default";
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]33 pinctrl-0 = <&pinctrl_sdmmc1_default>;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]34 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]36 };
37
38 apb {
39
40 uart1: serial@f8020000 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_uart1_default>;
43 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]44 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]45 };
46
47 i2c0: i2c@f8028000 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_i2c0_default>;
50 status = "okay";
51 };
52
53 i2c1: i2c@fc028000 {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_i2c1_default>;
56 status = "okay";
57
58 pmic@5b {
59 compatible = "active-semi,act8945a";
60 reg = <0x5b>;
61 active-semi,vsel-low;
62 status = "okay";
63 };
64 };
65
66 pit: timer@f8048030 {
67 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]68 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]69 };
70
71 sfr: sfr@f8030000 {
72 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]74 };
75
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]76 pioA: pinctrl@fc038000 {
77 pinctrl_sdmmc1_default: sdmmc1_default {
78 cmd_data {
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]79 pinmux = <PIN_PA28__SDMMC1_CMD>,
80 <PIN_PA18__SDMMC1_DAT0>,
81 <PIN_PA19__SDMMC1_DAT1>,
82 <PIN_PA20__SDMMC1_DAT2>,
83 <PIN_PA21__SDMMC1_DAT3>;
84 bias-pull-up;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]86 };
87
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]88 ck_cd {
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]89 pinmux = <PIN_PA22__SDMMC1_CK>,
90 <PIN_PA30__SDMMC1_CD>;
91 bias-disable;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-all;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]93 };
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]94 };
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]95
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]96 pinctrl_uart1_default: uart1_default {
97 pinmux = <PIN_PD2__URXD1>,
98 <PIN_PD3__UTXD1>;
99 bias-disable;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-all;
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]101 };
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]102
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]103 pinctrl_i2c0_default: i2c0_default {
104 pinmux = <PIN_PD21__TWD0>,
105 <PIN_PD22__TWCK0>;
106 bias-disable;
107 };
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]108
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]109 pinctrl_i2c1_default: i2c1_default {
110 pinmux = <PIN_PD4__TWD1>,
111 <PIN_PD5__TWCK1>;
112 bias-disable;
113 };
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]114
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]115 pinctrl_usb_default: usb_default {
116 pinmux = <PIN_PB10__GPIO>;
117 bias-disable;
118 };
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]119
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300[diff] [blame]120 pinctrl_usba_vbus: usba_vbus {
121 pinmux = <PIN_PA31__GPIO>;
122 bias-disable;
Greg Gallagher77450772021-01-21 11:55:34 -0500[diff] [blame]123 };
124 };
125 };
126 };
127};