blob: 5f78bc5ab905953795b944e3cd44ddc312979fec [file] [log] [blame]
Robert Markoe7a34f12020-07-06 10:37:54 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2019 Sartura Ltd.
4 *
5 * Author: Robert Marko <robert.marko@sartura.hr>
6 */
7
8 /dts-v1/;
9
10#include "skeleton.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 model = "Qualcomm Technologies, Inc. IPQ4019";
19 compatible = "qcom,ipq4019";
20
21 aliases {
22 serial0 = &blsp1_uart1;
23 };
24
25 reserved-memory {
26 #address-cells = <0x1>;
27 #size-cells = <0x1>;
28 ranges;
29
30 smem_mem: smem_region: smem@87e00000 {
31 reg = <0x87e00000 0x080000>;
32 no-map;
33 };
34
35 tz@87e80000 {
36 reg = <0x87e80000 0x180000>;
37 no-map;
38 };
39 };
40
41 soc: soc {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 ranges;
45 compatible = "simple-bus";
46
47 gcc: clock-controller@1800000 {
48 compatible = "qcom,gcc-ipq4019";
49 reg = <0x1800000 0x60000>;
50 #clock-cells = <1>;
51 #reset-cells = <1>;
52 u-boot,dm-pre-reloc;
53 };
54
55 pinctrl: qcom,tlmm@1000000 {
56 compatible = "qcom,tlmm-ipq4019";
57 reg = <0x1000000 0x300000>;
58 u-boot,dm-pre-reloc;
59 };
60
61 blsp1_uart1: serial@78af000 {
62 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
63 reg = <0x78af000 0x200>;
64 clock = <&gcc 26>;
65 bit-rate = <0xFF>;
66 status = "disabled";
67 u-boot,dm-pre-reloc;
68 };
69
70 soc_gpios: pinctrl@1000000 {
71 compatible = "qcom,ipq4019-pinctrl";
72 reg = <0x1000000 0x300000>;
73 gpio-controller;
74 gpio-count = <100>;
75 gpio-bank-name="soc";
76 #gpio-cells = <2>;
77 };
78 };
79};