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git01.mediatek.com / filogic / uboot / add61f21b2bd001ccaf1fdf61fbfc487fb024eb7 / . / arch / arm / dts / imx8mq-evk.dts
blob: 55294ba9c8798bd520336470cd4db40d84a4f016 [file] [log] [blame]
Patrick Wildt02548cf2019-10-14 13:19:00 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9/* First 128KB is for PSCI ATF. */
10/memreserve/ 0x40000000 0x00020000;
11
12#include "imx8mq.dtsi"
13
14/ {
15 model = "NXP i.MX8MQ EVK";
16 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0x00000000 0x40000000 0 0xc0000000>;
25 };
26
27 pcie0_refclk: pcie0-refclk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <100000000>;
31 };
32
33 reg_usdhc2_vmmc: regulator-vsd-3v3 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_reg_usdhc2>;
36 compatible = "regulator-fixed";
37 regulator-name = "VSD_3V3";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 enable-active-high;
42 };
43
44 buck2_reg: regulator-buck2 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_buck2>;
47 compatible = "regulator-gpio";
48 regulator-name = "vdd_arm";
49 regulator-min-microvolt = <900000>;
50 regulator-max-microvolt = <1000000>;
51 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
52 states = <1000000 0x0
53 900000 0x1>;
54 };
55
56 wm8524: audio-codec {
57 #sound-dai-cells = <0>;
58 compatible = "wlf,wm8524";
59 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
60 };
61
62 sound-wm8524 {
63 compatible = "simple-audio-card";
64 simple-audio-card,name = "wm8524-audio";
65 simple-audio-card,format = "i2s";
66 simple-audio-card,frame-master = <&cpudai>;
67 simple-audio-card,bitclock-master = <&cpudai>;
68 simple-audio-card,widgets =
69 "Line", "Left Line Out Jack",
70 "Line", "Right Line Out Jack";
71 simple-audio-card,routing =
72 "Left Line Out Jack", "LINEVOUTL",
73 "Right Line Out Jack", "LINEVOUTR";
74
75 cpudai: simple-audio-card,cpu {
76 sound-dai = <&sai2>;
77 };
78
79 link_codec: simple-audio-card,codec {
80 sound-dai = <&wm8524>;
81 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
82 };
83 };
84};
85
86&A53_0 {
87 cpu-supply = <&buck2_reg>;
88};
89
90&A53_1 {
91 cpu-supply = <&buck2_reg>;
92};
93
94&A53_2 {
95 cpu-supply = <&buck2_reg>;
96};
97
98&A53_3 {
99 cpu-supply = <&buck2_reg>;
100};
101
102&fec1 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_fec1>;
105 phy-mode = "rgmii-id";
106 phy-handle = <&ethphy0>;
Alifer Moraesc3dc3d22020-02-14 16:18:50 -0300[diff] [blame]107 phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
108 phy-reset-duration = <10>;
Patrick Wildt02548cf2019-10-14 13:19:00 +0200[diff] [blame]109 fsl,magic-packet;
110 status = "okay";
111
112 mdio {
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 ethphy0: ethernet-phy@0 {
117 compatible = "ethernet-phy-ieee802.3-c22";
118 reg = <0>;
119 };
120 };
121};
122
123&sai2 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_sai2>;
126 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
127 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
128 assigned-clock-rates = <0>, <24576000>;
129 status = "okay";
130};
131
132&gpio5 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_wifi_reset>;
135
136 wl-reg-on {
137 gpio-hog;
138 gpios = <29 GPIO_ACTIVE_HIGH>;
139 output-high;
140 };
141};
142
143&i2c1 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c1>;
147 status = "okay";
148
149 pmic@8 {
150 compatible = "fsl,pfuze100";
151 reg = <0x8>;
152
153 regulators {
154 sw1a_reg: sw1ab {
155 regulator-min-microvolt = <825000>;
156 regulator-max-microvolt = <1100000>;
157 };
158
159 sw1c_reg: sw1c {
160 regulator-min-microvolt = <825000>;
161 regulator-max-microvolt = <1100000>;
162 };
163
164 sw2_reg: sw2 {
165 regulator-min-microvolt = <1100000>;
166 regulator-max-microvolt = <1100000>;
167 regulator-always-on;
168 };
169
170 sw3a_reg: sw3ab {
171 regulator-min-microvolt = <825000>;
172 regulator-max-microvolt = <1100000>;
173 regulator-always-on;
174 };
175
176 sw4_reg: sw4 {
177 regulator-min-microvolt = <1800000>;
178 regulator-max-microvolt = <1800000>;
179 regulator-always-on;
180 };
181
182 swbst_reg: swbst {
183 regulator-min-microvolt = <5000000>;
184 regulator-max-microvolt = <5150000>;
185 };
186
187 snvs_reg: vsnvs {
188 regulator-min-microvolt = <1000000>;
189 regulator-max-microvolt = <3000000>;
190 regulator-always-on;
191 };
192
193 vref_reg: vrefddr {
194 regulator-always-on;
195 };
196
197 vgen1_reg: vgen1 {
198 regulator-min-microvolt = <800000>;
199 regulator-max-microvolt = <1550000>;
200 };
201
202 vgen2_reg: vgen2 {
203 regulator-min-microvolt = <850000>;
204 regulator-max-microvolt = <975000>;
205 regulator-always-on;
206 };
207
208 vgen3_reg: vgen3 {
209 regulator-min-microvolt = <1675000>;
210 regulator-max-microvolt = <1975000>;
211 regulator-always-on;
212 };
213
214 vgen4_reg: vgen4 {
215 regulator-min-microvolt = <1625000>;
216 regulator-max-microvolt = <1875000>;
217 regulator-always-on;
218 };
219
220 vgen5_reg: vgen5 {
221 regulator-min-microvolt = <3075000>;
222 regulator-max-microvolt = <3625000>;
223 regulator-always-on;
224 };
225
226 vgen6_reg: vgen6 {
227 regulator-min-microvolt = <1800000>;
228 regulator-max-microvolt = <3300000>;
229 };
230 };
231 };
232};
233
234&pcie0 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_pcie0>;
237 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
238 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
239 <&clk IMX8MQ_CLK_PCIE1_AUX>,
240 <&clk IMX8MQ_CLK_PCIE1_PHY>,
241 <&pcie0_refclk>;
242 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
243 status = "okay";
244};
245
246&pgc_gpu {
247 power-supply = <&sw1a_reg>;
248};
249
250&snvs_pwrkey {
251 status = "okay";
252};
253
254&uart1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart1>;
257 status = "okay";
258};
259
260&usb3_phy1 {
261 status = "okay";
262};
263
264&usb_dwc3_1 {
265 dr_mode = "host";
266 status = "okay";
267};
268
269&qspi0 {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_qspi>;
272 status = "okay";
273
274 n25q256a: flash@0 {
275 reg = <0>;
276 #address-cells = <1>;
277 #size-cells = <1>;
278 compatible = "micron,n25q256a", "jedec,spi-nor";
279 spi-max-frequency = <29000000>;
280 };
281};
282
283&usdhc1 {
284 pinctrl-names = "default", "state_100mhz", "state_200mhz";
285 pinctrl-0 = <&pinctrl_usdhc1>;
286 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
287 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
288 vqmmc-supply = <&sw4_reg>;
289 bus-width = <8>;
290 non-removable;
291 no-sd;
292 no-sdio;
293 status = "okay";
294};
295
296&usdhc2 {
297 pinctrl-names = "default", "state_100mhz", "state_200mhz";
298 pinctrl-0 = <&pinctrl_usdhc2>;
299 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
300 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
301 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
302 vmmc-supply = <&reg_usdhc2_vmmc>;
303 status = "okay";
304};
305
306&wdog1 {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_wdog>;
309 fsl,ext-reset-output;
310 status = "okay";
311};
312
313&iomuxc {
314 pinctrl_buck2: vddarmgrp {
315 fsl,pins = <
316 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
317 >;
318
319 };
320
321 pinctrl_fec1: fec1grp {
322 fsl,pins = <
323 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
324 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
325 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
326 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
327 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
328 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
329 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
330 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
331 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
332 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
333 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
334 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
335 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
336 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
337 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
338 >;
339 };
340
341 pinctrl_i2c1: i2c1grp {
342 fsl,pins = <
343 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
344 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
345 >;
346 };
347
348 pinctrl_pcie0: pcie0grp {
349 fsl,pins = <
350 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
351 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
352 >;
353 };
354
355 pinctrl_qspi: qspigrp {
356 fsl,pins = <
357 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
358 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
359 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
360 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
361 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
362 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
363
364 >;
365 };
366
367 pinctrl_reg_usdhc2: regusdhc2grpgpio {
368 fsl,pins = <
369 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
370 >;
371 };
372
373 pinctrl_sai2: sai2grp {
374 fsl,pins = <
375 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
376 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
377 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
378 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
379 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
380 >;
381 };
382
383 pinctrl_uart1: uart1grp {
384 fsl,pins = <
385 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
386 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
387 >;
388 };
389
390 pinctrl_usdhc1: usdhc1grp {
391 fsl,pins = <
392 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
393 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
394 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
395 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
396 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
397 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
398 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
399 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
400 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
401 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
402 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
403 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
404 >;
405 };
406
407 pinctrl_usdhc1_100mhz: usdhc1-100grp {
408 fsl,pins = <
409 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
410 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
411 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
412 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
413 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
414 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
415 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
416 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
417 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
418 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
419 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
420 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
421 >;
422 };
423
424 pinctrl_usdhc1_200mhz: usdhc1-200grp {
425 fsl,pins = <
426 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
427 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
428 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
429 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
430 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
431 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
432 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
433 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
434 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
435 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
436 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
437 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
438 >;
439 };
440
441 pinctrl_usdhc2: usdhc2grp {
442 fsl,pins = <
443 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
444 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
445 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
446 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
447 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
448 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
449 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
450 >;
451 };
452
453 pinctrl_usdhc2_100mhz: usdhc2-100grp {
454 fsl,pins = <
455 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
456 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
457 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
458 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
459 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
460 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
461 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
462 >;
463 };
464
465 pinctrl_usdhc2_200mhz: usdhc2-200grp {
466 fsl,pins = <
467 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
468 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
469 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
470 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
471 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
472 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
473 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
474 >;
475 };
476
477 pinctrl_wdog: wdog1grp {
478 fsl,pins = <
479 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
480 >;
481 };
482
483 pinctrl_wifi_reset: wifiresetgrp {
484 fsl,pins = <
485 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
486 >;
487 };
488};