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git01.mediatek.com / filogic / uboot / ad67972f39ada101144a14bd5b6a32957a1e3e15 / . / arch / arm / dts / imx8mm-kontron-bl-common-u-boot.dtsi
blob: 65dfd33725ee967f7b2591bcf9c3e12b9e041ac1 [file] [log] [blame]
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6#include "imx8mm-u-boot.dtsi"
7
8/ {
9 aliases {
10 usb0 = &usbotg1;
11 usb1 = &usbotg2;
12 };
13
14 wdt-reboot {
15 compatible = "wdt-reboot";
16 wdt = <&wdog1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]17 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]18 };
19
20 firmware {
21 optee {
22 compatible = "linaro,optee-tz";
23 method = "smc";
24 };
25 };
26};
27
28&crypto {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]30};
31
32&sec_jr0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]33 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]34};
35
36&sec_jr1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]37 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]38};
39
40&sec_jr2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]41 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]42};
43
44&i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
46 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]47};
48
49&i2c2 {
50 status = "okay";
Frieder Schrempf26e05b32022-08-24 15:59:20 +0200[diff] [blame]51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_i2c2>;
53};
54
55&iomuxc {
56 pinctrl_i2c2: i2c2grp {
57 fsl,pins = <
58 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
59 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
60 >;
61 };
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]62};
63
64&pinctrl_ecspi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]65 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]66};
67
68&pinctrl_i2c1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]69 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]70};
71
72&pinctrl_pmic {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]73 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]74};
75
76&pinctrl_uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-pre-ram;
78 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]79};
80
81&pinctrl_usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]83};
84
85&pinctrl_usdhc1_100mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]87};
88
89&pinctrl_usdhc1_200mhz {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]90 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]91};
92
93&pinctrl_usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]94 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]95};
96
97&pca9450 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]98 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]99};
100
101&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]103};
104
105&ecspi1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]106 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]107};
108
109&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]110 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]111};
112
113&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]115};
116
117&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]118 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]119};
120
121&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]122 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]123};
124
125&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]126 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]127};
128
129&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
131 bootph-all;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]132};
133
134&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]135 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]136};
137
138&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]139 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]140};
141
142&wdog1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]143 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]144};
145
146&pinctrl_wdog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]147 bootph-pre-ram;
Frieder Schrempf3048ecd2022-08-24 15:59:19 +0200[diff] [blame]148};