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git01.mediatek.com / filogic / uboot / ad20032f6f3e7067af4aeb97e5da41efa0a2ea19 / . / arch / arm / mach-apple / board.c
blob: 47393babbc62ae7abb5aa0d43b96c855526f4ebc [file] [log] [blame]
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
4 */
5
6#include <common.h>
7#include <dm.h>
Mark Kettenisdfacafb2022-04-19 21:20:31 +0200[diff] [blame]8#include <dm/uclass-internal.h>
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]9#include <efi_loader.h>
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]10#include <lmb.h>
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]11
12#include <asm/armv8/mmu.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
15#include <asm/system.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
Janne Grunau430ff522022-07-01 00:06:17 +0200[diff] [blame]19/* Apple M1/M2 */
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]20
21static struct mm_region t8103_mem_map[] = {
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]22 {
23 /* I/O */
24 .virt = 0x200000000,
25 .phys = 0x200000000,
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]26 .size = 2UL * SZ_1G,
27 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
28 PTE_BLOCK_NON_SHARE |
29 PTE_BLOCK_PXN | PTE_BLOCK_UXN
30 }, {
31 /* I/O */
32 .virt = 0x380000000,
33 .phys = 0x380000000,
34 .size = SZ_1G,
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]35 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
36 PTE_BLOCK_NON_SHARE |
37 PTE_BLOCK_PXN | PTE_BLOCK_UXN
38 }, {
39 /* I/O */
40 .virt = 0x500000000,
41 .phys = 0x500000000,
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]42 .size = SZ_1G,
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]43 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
44 PTE_BLOCK_NON_SHARE |
45 PTE_BLOCK_PXN | PTE_BLOCK_UXN
46 }, {
47 /* I/O */
48 .virt = 0x680000000,
49 .phys = 0x680000000,
50 .size = SZ_512M,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
54 }, {
55 /* PCIE */
56 .virt = 0x6a0000000,
57 .phys = 0x6a0000000,
58 .size = SZ_512M,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
60 PTE_BLOCK_INNER_SHARE |
61 PTE_BLOCK_PXN | PTE_BLOCK_UXN
62 }, {
63 /* PCIE */
64 .virt = 0x6c0000000,
65 .phys = 0x6c0000000,
66 .size = SZ_1G,
67 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
68 PTE_BLOCK_INNER_SHARE |
69 PTE_BLOCK_PXN | PTE_BLOCK_UXN
70 }, {
71 /* RAM */
72 .virt = 0x800000000,
73 .phys = 0x800000000,
74 .size = 8UL * SZ_1G,
75 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
76 PTE_BLOCK_INNER_SHARE
77 }, {
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]78 /* Framebuffer */
79 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
80 PTE_BLOCK_INNER_SHARE |
81 PTE_BLOCK_PXN | PTE_BLOCK_UXN
82 }, {
83 /* List terminator */
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]84 0,
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]85 }
86};
87
88/* Apple M1 Pro/Max */
89
90static struct mm_region t6000_mem_map[] = {
91 {
92 /* I/O */
93 .virt = 0x280000000,
94 .phys = 0x280000000,
95 .size = SZ_1G,
96 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
97 PTE_BLOCK_NON_SHARE |
98 PTE_BLOCK_PXN | PTE_BLOCK_UXN
99 }, {
100 /* I/O */
101 .virt = 0x380000000,
102 .phys = 0x380000000,
103 .size = SZ_1G,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
105 PTE_BLOCK_NON_SHARE |
106 PTE_BLOCK_PXN | PTE_BLOCK_UXN
107 }, {
108 /* I/O */
109 .virt = 0x580000000,
110 .phys = 0x580000000,
111 .size = SZ_512M,
112 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
113 PTE_BLOCK_NON_SHARE |
114 PTE_BLOCK_PXN | PTE_BLOCK_UXN
115 }, {
116 /* PCIE */
117 .virt = 0x5a0000000,
118 .phys = 0x5a0000000,
119 .size = SZ_512M,
120 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
121 PTE_BLOCK_INNER_SHARE |
122 PTE_BLOCK_PXN | PTE_BLOCK_UXN
123 }, {
124 /* PCIE */
125 .virt = 0x5c0000000,
126 .phys = 0x5c0000000,
127 .size = SZ_1G,
128 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
129 PTE_BLOCK_INNER_SHARE |
130 PTE_BLOCK_PXN | PTE_BLOCK_UXN
131 }, {
132 /* I/O */
133 .virt = 0x700000000,
134 .phys = 0x700000000,
135 .size = SZ_1G,
136 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
137 PTE_BLOCK_NON_SHARE |
138 PTE_BLOCK_PXN | PTE_BLOCK_UXN
139 }, {
140 /* I/O */
141 .virt = 0xb00000000,
142 .phys = 0xb00000000,
143 .size = SZ_1G,
144 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
145 PTE_BLOCK_NON_SHARE |
146 PTE_BLOCK_PXN | PTE_BLOCK_UXN
147 }, {
148 /* I/O */
149 .virt = 0xf00000000,
150 .phys = 0xf00000000,
151 .size = SZ_1G,
152 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
153 PTE_BLOCK_NON_SHARE |
154 PTE_BLOCK_PXN | PTE_BLOCK_UXN
155 }, {
156 /* I/O */
157 .virt = 0x1300000000,
158 .phys = 0x1300000000,
159 .size = SZ_1G,
160 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
161 PTE_BLOCK_NON_SHARE |
162 PTE_BLOCK_PXN | PTE_BLOCK_UXN
163 }, {
164 /* RAM */
165 .virt = 0x10000000000,
166 .phys = 0x10000000000,
167 .size = 16UL * SZ_1G,
168 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
169 PTE_BLOCK_INNER_SHARE
170 }, {
171 /* Framebuffer */
172 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
173 PTE_BLOCK_INNER_SHARE |
174 PTE_BLOCK_PXN | PTE_BLOCK_UXN
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]175 }, {
176 /* List terminator */
177 0,
178 }
179};
180
Janne Grunaudc174322022-03-29 13:29:35 +0200[diff] [blame]181/* Apple M1 Ultra */
182
183static struct mm_region t6002_mem_map[] = {
184 {
185 /* I/O */
186 .virt = 0x280000000,
187 .phys = 0x280000000,
188 .size = SZ_1G,
189 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
190 PTE_BLOCK_NON_SHARE |
191 PTE_BLOCK_PXN | PTE_BLOCK_UXN
192 }, {
193 /* I/O */
194 .virt = 0x380000000,
195 .phys = 0x380000000,
196 .size = SZ_1G,
197 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
198 PTE_BLOCK_NON_SHARE |
199 PTE_BLOCK_PXN | PTE_BLOCK_UXN
200 }, {
201 /* I/O */
202 .virt = 0x580000000,
203 .phys = 0x580000000,
204 .size = SZ_512M,
205 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
206 PTE_BLOCK_NON_SHARE |
207 PTE_BLOCK_PXN | PTE_BLOCK_UXN
208 }, {
209 /* PCIE */
210 .virt = 0x5a0000000,
211 .phys = 0x5a0000000,
212 .size = SZ_512M,
213 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
214 PTE_BLOCK_INNER_SHARE |
215 PTE_BLOCK_PXN | PTE_BLOCK_UXN
216 }, {
217 /* PCIE */
218 .virt = 0x5c0000000,
219 .phys = 0x5c0000000,
220 .size = SZ_1G,
221 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
222 PTE_BLOCK_INNER_SHARE |
223 PTE_BLOCK_PXN | PTE_BLOCK_UXN
224 }, {
225 /* I/O */
226 .virt = 0x700000000,
227 .phys = 0x700000000,
228 .size = SZ_1G,
229 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230 PTE_BLOCK_NON_SHARE |
231 PTE_BLOCK_PXN | PTE_BLOCK_UXN
232 }, {
233 /* I/O */
234 .virt = 0xb00000000,
235 .phys = 0xb00000000,
236 .size = SZ_1G,
237 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
238 PTE_BLOCK_NON_SHARE |
239 PTE_BLOCK_PXN | PTE_BLOCK_UXN
240 }, {
241 /* I/O */
242 .virt = 0xf00000000,
243 .phys = 0xf00000000,
244 .size = SZ_1G,
245 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
246 PTE_BLOCK_NON_SHARE |
247 PTE_BLOCK_PXN | PTE_BLOCK_UXN
248 }, {
249 /* I/O */
250 .virt = 0x1300000000,
251 .phys = 0x1300000000,
252 .size = SZ_1G,
253 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
254 PTE_BLOCK_NON_SHARE |
255 PTE_BLOCK_PXN | PTE_BLOCK_UXN
256 }, {
257 /* I/O */
258 .virt = 0x2280000000,
259 .phys = 0x2280000000,
260 .size = SZ_1G,
261 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
262 PTE_BLOCK_NON_SHARE |
263 PTE_BLOCK_PXN | PTE_BLOCK_UXN
264 }, {
265 /* I/O */
266 .virt = 0x2380000000,
267 .phys = 0x2380000000,
268 .size = SZ_1G,
269 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
270 PTE_BLOCK_NON_SHARE |
271 PTE_BLOCK_PXN | PTE_BLOCK_UXN
272 }, {
273 /* I/O */
274 .virt = 0x2580000000,
275 .phys = 0x2580000000,
276 .size = SZ_512M,
277 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
278 PTE_BLOCK_NON_SHARE |
279 PTE_BLOCK_PXN | PTE_BLOCK_UXN
280 }, {
281 /* PCIE */
282 .virt = 0x25a0000000,
283 .phys = 0x25a0000000,
284 .size = SZ_512M,
285 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
286 PTE_BLOCK_INNER_SHARE |
287 PTE_BLOCK_PXN | PTE_BLOCK_UXN
288 }, {
289 /* PCIE */
290 .virt = 0x25c0000000,
291 .phys = 0x25c0000000,
292 .size = SZ_1G,
293 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
294 PTE_BLOCK_INNER_SHARE |
295 PTE_BLOCK_PXN | PTE_BLOCK_UXN
296 }, {
297 /* I/O */
298 .virt = 0x2700000000,
299 .phys = 0x2700000000,
300 .size = SZ_1G,
301 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
302 PTE_BLOCK_NON_SHARE |
303 PTE_BLOCK_PXN | PTE_BLOCK_UXN
304 }, {
305 /* I/O */
306 .virt = 0x2b00000000,
307 .phys = 0x2b00000000,
308 .size = SZ_1G,
309 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
310 PTE_BLOCK_NON_SHARE |
311 PTE_BLOCK_PXN | PTE_BLOCK_UXN
312 }, {
313 /* I/O */
314 .virt = 0x2f00000000,
315 .phys = 0x2f00000000,
316 .size = SZ_1G,
317 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE |
319 PTE_BLOCK_PXN | PTE_BLOCK_UXN
320 }, {
321 /* I/O */
322 .virt = 0x3300000000,
323 .phys = 0x3300000000,
324 .size = SZ_1G,
325 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
326 PTE_BLOCK_NON_SHARE |
327 PTE_BLOCK_PXN | PTE_BLOCK_UXN
328 }, {
329 /* RAM */
330 .virt = 0x10000000000,
331 .phys = 0x10000000000,
332 .size = 16UL * SZ_1G,
333 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
334 PTE_BLOCK_INNER_SHARE
335 }, {
336 /* Framebuffer */
337 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
338 PTE_BLOCK_INNER_SHARE |
339 PTE_BLOCK_PXN | PTE_BLOCK_UXN
340 }, {
341 /* List terminator */
342 0,
343 }
344};
345
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]346/* Apple M2 Pro/Max */
347
348static struct mm_region t6020_mem_map[] = {
349 {
350 /* I/O */
351 .virt = 0x280000000,
352 .phys = 0x280000000,
353 .size = SZ_1G,
354 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
355 PTE_BLOCK_NON_SHARE |
356 PTE_BLOCK_PXN | PTE_BLOCK_UXN
357 }, {
358 /* I/O */
359 .virt = 0x340000000,
360 .phys = 0x340000000,
361 .size = SZ_1G,
362 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
363 PTE_BLOCK_NON_SHARE |
364 PTE_BLOCK_PXN | PTE_BLOCK_UXN
365 }, {
366 /* I/O */
367 .virt = 0x380000000,
368 .phys = 0x380000000,
369 .size = SZ_1G,
370 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
371 PTE_BLOCK_NON_SHARE |
372 PTE_BLOCK_PXN | PTE_BLOCK_UXN
373 }, {
374 /* I/O */
375 .virt = 0x580000000,
376 .phys = 0x580000000,
377 .size = SZ_512M,
378 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
379 PTE_BLOCK_NON_SHARE |
380 PTE_BLOCK_PXN | PTE_BLOCK_UXN
381 }, {
382 /* PCIE */
383 .virt = 0x5a0000000,
384 .phys = 0x5a0000000,
385 .size = SZ_512M,
386 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
387 PTE_BLOCK_INNER_SHARE |
388 PTE_BLOCK_PXN | PTE_BLOCK_UXN
389 }, {
390 /* PCIE */
391 .virt = 0x5c0000000,
392 .phys = 0x5c0000000,
393 .size = SZ_1G,
394 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
395 PTE_BLOCK_INNER_SHARE |
396 PTE_BLOCK_PXN | PTE_BLOCK_UXN
397 }, {
398 /* I/O */
399 .virt = 0x700000000,
400 .phys = 0x700000000,
401 .size = SZ_1G,
402 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
403 PTE_BLOCK_NON_SHARE |
404 PTE_BLOCK_PXN | PTE_BLOCK_UXN
405 }, {
406 /* I/O */
407 .virt = 0xb00000000,
408 .phys = 0xb00000000,
409 .size = SZ_1G,
410 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
411 PTE_BLOCK_NON_SHARE |
412 PTE_BLOCK_PXN | PTE_BLOCK_UXN
413 }, {
414 /* I/O */
415 .virt = 0xf00000000,
416 .phys = 0xf00000000,
417 .size = SZ_1G,
418 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
419 PTE_BLOCK_NON_SHARE |
420 PTE_BLOCK_PXN | PTE_BLOCK_UXN
421 }, {
422 /* I/O */
423 .virt = 0x1300000000,
424 .phys = 0x1300000000,
425 .size = SZ_1G,
426 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
427 PTE_BLOCK_NON_SHARE |
428 PTE_BLOCK_PXN | PTE_BLOCK_UXN
429 }, {
430 /* RAM */
431 .virt = 0x10000000000,
432 .phys = 0x10000000000,
433 .size = 16UL * SZ_1G,
434 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
435 PTE_BLOCK_INNER_SHARE
436 }, {
437 /* Framebuffer */
438 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
439 PTE_BLOCK_INNER_SHARE |
440 PTE_BLOCK_PXN | PTE_BLOCK_UXN
441 }, {
442 /* List terminator */
443 0,
444 }
445};
446
Janne Grunau19e1c482023-09-06 23:50:34 +0200[diff] [blame]447/* Apple M2 Ultra */
448
449static struct mm_region t6022_mem_map[] = {
450 {
451 /* I/O */
452 .virt = 0x280000000,
453 .phys = 0x280000000,
454 .size = SZ_1G,
455 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
456 PTE_BLOCK_NON_SHARE |
457 PTE_BLOCK_PXN | PTE_BLOCK_UXN
458 }, {
459 /* I/O */
460 .virt = 0x340000000,
461 .phys = 0x340000000,
462 .size = SZ_1G,
463 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
464 PTE_BLOCK_NON_SHARE |
465 PTE_BLOCK_PXN | PTE_BLOCK_UXN
466 }, {
467 /* I/O */
468 .virt = 0x380000000,
469 .phys = 0x380000000,
470 .size = SZ_1G,
471 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
472 PTE_BLOCK_NON_SHARE |
473 PTE_BLOCK_PXN | PTE_BLOCK_UXN
474 }, {
475 /* I/O */
476 .virt = 0x580000000,
477 .phys = 0x580000000,
478 .size = SZ_512M,
479 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
480 PTE_BLOCK_NON_SHARE |
481 PTE_BLOCK_PXN | PTE_BLOCK_UXN
482 }, {
483 /* PCIE */
484 .virt = 0x5a0000000,
485 .phys = 0x5a0000000,
486 .size = SZ_512M,
487 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
488 PTE_BLOCK_INNER_SHARE |
489 PTE_BLOCK_PXN | PTE_BLOCK_UXN
490 }, {
491 /* PCIE */
492 .virt = 0x5c0000000,
493 .phys = 0x5c0000000,
494 .size = SZ_1G,
495 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
496 PTE_BLOCK_INNER_SHARE |
497 PTE_BLOCK_PXN | PTE_BLOCK_UXN
498 }, {
499 /* I/O */
500 .virt = 0x700000000,
501 .phys = 0x700000000,
502 .size = SZ_1G,
503 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
504 PTE_BLOCK_NON_SHARE |
505 PTE_BLOCK_PXN | PTE_BLOCK_UXN
506 }, {
507 /* I/O */
508 .virt = 0xb00000000,
509 .phys = 0xb00000000,
510 .size = SZ_1G,
511 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
512 PTE_BLOCK_NON_SHARE |
513 PTE_BLOCK_PXN | PTE_BLOCK_UXN
514 }, {
515 /* I/O */
516 .virt = 0xf00000000,
517 .phys = 0xf00000000,
518 .size = SZ_1G,
519 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
520 PTE_BLOCK_NON_SHARE |
521 PTE_BLOCK_PXN | PTE_BLOCK_UXN
522 }, {
523 /* I/O */
524 .virt = 0x1300000000,
525 .phys = 0x1300000000,
526 .size = SZ_1G,
527 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
528 PTE_BLOCK_NON_SHARE |
529 PTE_BLOCK_PXN | PTE_BLOCK_UXN
530 }, {
531 /* I/O */
532 .virt = 0x2280000000,
533 .phys = 0x2280000000,
534 .size = SZ_1G,
535 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
536 PTE_BLOCK_NON_SHARE |
537 PTE_BLOCK_PXN | PTE_BLOCK_UXN
538 }, {
539 /* I/O */
540 .virt = 0x2340000000,
541 .phys = 0x2340000000,
542 .size = SZ_1G,
543 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
544 PTE_BLOCK_NON_SHARE |
545 PTE_BLOCK_PXN | PTE_BLOCK_UXN
546 }, {
547 /* I/O */
548 .virt = 0x2380000000,
549 .phys = 0x2380000000,
550 .size = SZ_1G,
551 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
552 PTE_BLOCK_NON_SHARE |
553 PTE_BLOCK_PXN | PTE_BLOCK_UXN
554 }, {
555 /* I/O */
556 .virt = 0x2580000000,
557 .phys = 0x2580000000,
558 .size = SZ_512M,
559 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
560 PTE_BLOCK_NON_SHARE |
561 PTE_BLOCK_PXN | PTE_BLOCK_UXN
562 }, {
563 /* PCIE */
564 .virt = 0x25a0000000,
565 .phys = 0x25a0000000,
566 .size = SZ_512M,
567 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
568 PTE_BLOCK_INNER_SHARE |
569 PTE_BLOCK_PXN | PTE_BLOCK_UXN
570 }, {
571 /* PCIE */
572 .virt = 0x25c0000000,
573 .phys = 0x25c0000000,
574 .size = SZ_1G,
575 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
576 PTE_BLOCK_INNER_SHARE |
577 PTE_BLOCK_PXN | PTE_BLOCK_UXN
578 }, {
579 /* I/O */
580 .virt = 0x2700000000,
581 .phys = 0x2700000000,
582 .size = SZ_1G,
583 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
584 PTE_BLOCK_NON_SHARE |
585 PTE_BLOCK_PXN | PTE_BLOCK_UXN
586 }, {
587 /* I/O */
588 .virt = 0x2b00000000,
589 .phys = 0x2b00000000,
590 .size = SZ_1G,
591 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
592 PTE_BLOCK_NON_SHARE |
593 PTE_BLOCK_PXN | PTE_BLOCK_UXN
594 }, {
595 /* I/O */
596 .virt = 0x2f00000000,
597 .phys = 0x2f00000000,
598 .size = SZ_1G,
599 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
600 PTE_BLOCK_NON_SHARE |
601 PTE_BLOCK_PXN | PTE_BLOCK_UXN
602 }, {
603 /* I/O */
604 .virt = 0x3300000000,
605 .phys = 0x3300000000,
606 .size = SZ_1G,
607 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
608 PTE_BLOCK_NON_SHARE |
609 PTE_BLOCK_PXN | PTE_BLOCK_UXN
610 }, {
611 /* RAM */
612 .virt = 0x10000000000,
613 .phys = 0x10000000000,
614 .size = 16UL * SZ_1G,
615 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
616 PTE_BLOCK_INNER_SHARE
617 }, {
618 /* Framebuffer */
619 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
620 PTE_BLOCK_INNER_SHARE |
621 PTE_BLOCK_PXN | PTE_BLOCK_UXN
622 }, {
623 /* List terminator */
624 0,
625 }
626};
627
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]628struct mm_region *mem_map;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]629
630int board_init(void)
631{
632 return 0;
633}
634
635int dram_init(void)
636{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]637 return fdtdec_setup_mem_size_base();
638}
639
640int dram_init_banksize(void)
641{
642 return fdtdec_setup_memory_banksize();
643}
644
645extern long fw_dtb_pointer;
646
647void *board_fdt_blob_setup(int *err)
648{
649 /* Return DTB pointer passed by m1n1 */
650 *err = 0;
651 return (void *)fw_dtb_pointer;
652}
653
654void build_mem_map(void)
655{
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]656 ofnode node;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]657 fdt_addr_t base;
658 fdt_size_t size;
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]659 int i;
660
Janne Grunau430ff522022-07-01 00:06:17 +0200[diff] [blame]661 if (of_machine_is_compatible("apple,t8103") ||
662 of_machine_is_compatible("apple,t8112"))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]663 mem_map = t8103_mem_map;
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]664 else if (of_machine_is_compatible("apple,t6000") ||
665 of_machine_is_compatible("apple,t6001"))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]666 mem_map = t6000_mem_map;
Janne Grunaudc174322022-03-29 13:29:35 +0200[diff] [blame]667 else if (of_machine_is_compatible("apple,t6002"))
668 mem_map = t6002_mem_map;
Mark Kettenis1b350702023-05-02 21:30:40 +0200[diff] [blame]669 else if (of_machine_is_compatible("apple,t6020") ||
670 of_machine_is_compatible("apple,t6021"))
671 mem_map = t6020_mem_map;
Janne Grunau19e1c482023-09-06 23:50:34 +0200[diff] [blame]672 else if (of_machine_is_compatible("apple,t6022"))
673 mem_map = t6022_mem_map;
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]674 else
675 panic("Unsupported SoC\n");
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]676
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]677 /* Find list terminator. */
678 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
679 ;
680
681 /* Align RAM mapping to page boundaries */
682 base = gd->bd->bi_dram[0].start;
683 size = gd->bd->bi_dram[0].size;
684 size += (base - ALIGN_DOWN(base, SZ_4K));
685 base = ALIGN_DOWN(base, SZ_4K);
686 size = ALIGN(size, SZ_4K);
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]687
688 /* Update RAM mapping */
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]689 mem_map[i - 2].virt = base;
690 mem_map[i - 2].phys = base;
691 mem_map[i - 2].size = size;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]692
693 node = ofnode_path("/chosen/framebuffer");
694 if (!ofnode_valid(node))
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]695 return;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]696
697 base = ofnode_get_addr_size(node, "reg", &size);
698 if (base == FDT_ADDR_T_NONE)
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]699 return;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]700
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]701 /* Align framebuffer mapping to page boundaries */
702 size += (base - ALIGN_DOWN(base, SZ_4K));
703 base = ALIGN_DOWN(base, SZ_4K);
704 size = ALIGN(size, SZ_4K);
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]705
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]706 /* Add framebuffer mapping */
707 mem_map[i - 1].virt = base;
708 mem_map[i - 1].phys = base;
709 mem_map[i - 1].size = size;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]710}
711
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]712void enable_caches(void)
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]713{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]714 build_mem_map();
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]715
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]716 icache_enable();
717 dcache_enable();
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]718}
719
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]720u64 get_page_table_size(void)
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]721{
Mark Kettenis73c82c82022-02-08 22:00:09 +0100[diff] [blame]722 return SZ_256K;
Mark Kettenis58d51272021-10-23 16:58:03 +0200[diff] [blame]723}
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]724
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]725#define KERNEL_COMP_SIZE SZ_128M
726
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]727int board_late_init(void)
728{
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]729 struct lmb lmb;
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]730 u32 status = 0;
731
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]732 lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]733
734 /* somewhat based on the Linux Kernel boot requirements:
735 * align by 2M and maximal FDT size 2M
736 */
Mark Kettenis74ec0482022-03-21 22:41:18 +0100[diff] [blame]737 status |= env_set_hex("loadaddr", lmb_alloc(&lmb, SZ_1G, SZ_2M));
738 status |= env_set_hex("fdt_addr_r", lmb_alloc(&lmb, SZ_2M, SZ_2M));
739 status |= env_set_hex("kernel_addr_r", lmb_alloc(&lmb, SZ_128M, SZ_2M));
740 status |= env_set_hex("ramdisk_addr_r", lmb_alloc(&lmb, SZ_1G, SZ_2M));
741 status |= env_set_hex("kernel_comp_addr_r",
742 lmb_alloc(&lmb, KERNEL_COMP_SIZE, SZ_2M));
743 status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
744 status |= env_set_hex("scriptaddr", lmb_alloc(&lmb, SZ_4M, SZ_2M));
745 status |= env_set_hex("pxefile_addr_r", lmb_alloc(&lmb, SZ_4M, SZ_2M));
Janne Grunau3a216712022-02-19 14:05:19 +0100[diff] [blame]746
747 if (status)
748 log_warning("late_init: Failed to set run time variables\n");
749
750 return 0;
751}
Mark Kettenisdfacafb2022-04-19 21:20:31 +0200[diff] [blame]752
753int ft_board_setup(void *blob, struct bd_info *bd)
754{
755 struct udevice *dev;
756 const char *stdoutname;
757 int node, ret;
758
759 /*
760 * Modify the "stdout-path" property under "/chosen" to point
761 * at "/chosen/framebuffer if a keyboard is available and
762 * we're not running under the m1n1 hypervisor.
763 * Developers can override this behaviour by dropping
764 * "vidconsole" from the "stdout" environment variable.
765 */
766
767 /* EL1 means we're running under the m1n1 hypervisor. */
768 if (current_el() == 1)
769 return 0;
770
771 ret = uclass_find_device(UCLASS_KEYBOARD, 0, &dev);
772 if (ret < 0)
773 return 0;
774
775 stdoutname = env_get("stdout");
776 if (!stdoutname || !strstr(stdoutname, "vidconsole"))
777 return 0;
778
779 /* Make sure we actually have a framebuffer. */
780 node = fdt_path_offset(blob, "/chosen/framebuffer");
781 if (node < 0 || !fdtdec_get_is_enabled(blob, node))
782 return 0;
783
784 node = fdt_path_offset(blob, "/chosen");
785 if (node < 0)
786 return 0;
787 fdt_setprop_string(blob, node, "stdout-path", "/chosen/framebuffer");
788
789 return 0;
790}