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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk5b845b62002-08-21 21:57:24 +00002/*
wdenk9b7f3842003-10-09 20:09:04 +00003 * (C) Copyright 2003
4 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
5 *
wdenk5b845b62002-08-21 21:57:24 +00006 * (C) Copyright 2002
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk5b845b62002-08-21 21:57:24 +00008 */
9
10/*
wdenk5b845b62002-08-21 21:57:24 +000011 * Altera FPGA support
12 */
13#include <common.h>
Marek Vasutb9d4df32014-09-16 20:33:54 +020014#include <errno.h>
wdenk9b7f3842003-10-09 20:09:04 +000015#include <ACEX1K.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
eran liberty4c373a92008-03-27 00:50:49 +010017#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000018
Marek Vasut9e3a8442014-09-16 20:21:42 +020019/* Define FPGA_DEBUG to 1 to get debug printf's */
20#define FPGA_DEBUG 0
wdenk5b845b62002-08-21 21:57:24 +000021
Marek Vasutf5d25e42014-09-16 21:17:51 +020022static const struct altera_fpga {
23 enum altera_family family;
24 const char *name;
25 int (*load)(Altera_desc *, const void *, size_t);
26 int (*dump)(Altera_desc *, const void *, size_t);
27 int (*info)(Altera_desc *);
28} altera_fpga[] = {
29#if defined(CONFIG_FPGA_ACEX1K)
30 { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
31 { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info },
32#elif defined(CONFIG_FPGA_CYCLON2)
33 { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
34 { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info },
35#endif
36#if defined(CONFIG_FPGA_STRATIX_II)
37 { Altera_StratixII, "StratixII", StratixII_load,
38 StratixII_dump, StratixII_info },
39#endif
Stefan Roesed919d722016-02-12 13:48:02 +010040#if defined(CONFIG_FPGA_STRATIX_V)
41 { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
42#endif
Pavel Machekc7213802014-09-08 14:08:45 +020043#if defined(CONFIG_FPGA_SOCFPGA)
44 { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
45#endif
Chee Hong Ang14192452020-08-07 11:50:03 +080046#if defined(CONFIG_FPGA_INTEL_SDM_MAILBOX)
47 { Intel_FPGA_SDM_Mailbox, "Intel SDM Mailbox", intel_sdm_mb_load, NULL,
48 NULL },
49#endif
Marek Vasutf5d25e42014-09-16 21:17:51 +020050};
51
Marek Vasutff4072c2014-09-16 20:32:51 +020052static int altera_validate(Altera_desc *desc, const char *fn)
53{
54 if (!desc) {
55 printf("%s: NULL descriptor!\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020056 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020057 }
58
59 if ((desc->family < min_altera_type) ||
60 (desc->family > max_altera_type)) {
61 printf("%s: Invalid family type, %d\n", fn, desc->family);
Marek Vasutb9d4df32014-09-16 20:33:54 +020062 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020063 }
64
65 if ((desc->iface < min_altera_iface_type) ||
66 (desc->iface > max_altera_iface_type)) {
67 printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
Marek Vasutb9d4df32014-09-16 20:33:54 +020068 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020069 }
70
71 if (!desc->size) {
72 printf("%s: NULL part size\n", fn);
Marek Vasutb9d4df32014-09-16 20:33:54 +020073 return -EINVAL;
Marek Vasutff4072c2014-09-16 20:32:51 +020074 }
75
Marek Vasutb9d4df32014-09-16 20:33:54 +020076 return 0;
Marek Vasutff4072c2014-09-16 20:32:51 +020077}
wdenk9b7f3842003-10-09 20:09:04 +000078
Marek Vasutf5d25e42014-09-16 21:17:51 +020079static const struct altera_fpga *
80altera_desc_to_fpga(Altera_desc *desc, const char *fn)
wdenk5b845b62002-08-21 21:57:24 +000081{
Marek Vasutf5d25e42014-09-16 21:17:51 +020082 int i;
wdenk9b7f3842003-10-09 20:09:04 +000083
Marek Vasutf5d25e42014-09-16 21:17:51 +020084 if (altera_validate(desc, fn)) {
85 printf("%s: Invalid device descriptor\n", fn);
86 return NULL;
Marek Vasut18221352014-09-16 20:29:24 +020087 }
88
Marek Vasutf5d25e42014-09-16 21:17:51 +020089 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) {
90 if (desc->family == altera_fpga[i].family)
91 break;
92 }
wdenk9b7f3842003-10-09 20:09:04 +000093
Marek Vasutf5d25e42014-09-16 21:17:51 +020094 if (i == ARRAY_SIZE(altera_fpga)) {
95 printf("%s: Unsupported family type, %d\n", fn, desc->family);
96 return NULL;
wdenk9b7f3842003-10-09 20:09:04 +000097 }
98
Marek Vasutf5d25e42014-09-16 21:17:51 +020099 return &altera_fpga[i];
wdenk5b845b62002-08-21 21:57:24 +0000100}
101
Marek Vasutf5d25e42014-09-16 21:17:51 +0200102int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
wdenk5b845b62002-08-21 21:57:24 +0000103{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200104 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000105
Marek Vasutf5d25e42014-09-16 21:17:51 +0200106 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200107 return FPGA_FAIL;
Marek Vasut18221352014-09-16 20:29:24 +0200108
Marek Vasutf5d25e42014-09-16 21:17:51 +0200109 debug_cond(FPGA_DEBUG, "%s: Launching the %s Loader...\n",
110 __func__, fpga->name);
111 if (fpga->load)
112 return fpga->load(desc, buf, bsize);
113 return 0;
114}
wdenk9b7f3842003-10-09 20:09:04 +0000115
Marek Vasutf5d25e42014-09-16 21:17:51 +0200116int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
117{
118 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000119
Marek Vasutf5d25e42014-09-16 21:17:51 +0200120 if (!fpga)
121 return FPGA_FAIL;
122
123 debug_cond(FPGA_DEBUG, "%s: Launching the %s Reader...\n",
124 __func__, fpga->name);
125 if (fpga->dump)
126 return fpga->dump(desc, buf, bsize);
127 return 0;
wdenk5b845b62002-08-21 21:57:24 +0000128}
129
Marek Vasut18221352014-09-16 20:29:24 +0200130int altera_info(Altera_desc *desc)
wdenk5b845b62002-08-21 21:57:24 +0000131{
Marek Vasutf5d25e42014-09-16 21:17:51 +0200132 const struct altera_fpga *fpga = altera_desc_to_fpga(desc, __func__);
wdenk9b7f3842003-10-09 20:09:04 +0000133
Marek Vasutf5d25e42014-09-16 21:17:51 +0200134 if (!fpga)
Marek Vasut18221352014-09-16 20:29:24 +0200135 return FPGA_FAIL;
wdenk9b7f3842003-10-09 20:09:04 +0000136
Marek Vasutf5d25e42014-09-16 21:17:51 +0200137 printf("Family: \t%s\n", fpga->name);
wdenk9b7f3842003-10-09 20:09:04 +0000138
Marek Vasut18221352014-09-16 20:29:24 +0200139 printf("Interface type:\t");
140 switch (desc->iface) {
141 case passive_serial:
142 printf("Passive Serial (PS)\n");
143 break;
144 case passive_parallel_synchronous:
145 printf("Passive Parallel Synchronous (PPS)\n");
146 break;
147 case passive_parallel_asynchronous:
148 printf("Passive Parallel Asynchronous (PPA)\n");
149 break;
150 case passive_serial_asynchronous:
151 printf("Passive Serial Asynchronous (PSA)\n");
152 break;
153 case altera_jtag_mode: /* Not used */
154 printf("JTAG Mode\n");
155 break;
156 case fast_passive_parallel:
157 printf("Fast Passive Parallel (FPP)\n");
158 break;
159 case fast_passive_parallel_security:
160 printf("Fast Passive Parallel with Security (FPPS)\n");
161 break;
Ang, Chee Hongff14f162018-12-19 18:35:15 -0800162 case secure_device_manager_mailbox:
163 puts("Secure Device Manager (SDM) Mailbox\n");
164 break;
Marek Vasut18221352014-09-16 20:29:24 +0200165 /* Add new interface types here */
166 default:
167 printf("Unsupported interface type, %d\n", desc->iface);
168 }
169
170 printf("Device Size: \t%zd bytes\n"
171 "Cookie: \t0x%x (%d)\n",
172 desc->size, desc->cookie, desc->cookie);
wdenk9b7f3842003-10-09 20:09:04 +0000173
Marek Vasut18221352014-09-16 20:29:24 +0200174 if (desc->iface_fns) {
175 printf("Device Function Table @ 0x%p\n", desc->iface_fns);
Marek Vasutf5d25e42014-09-16 21:17:51 +0200176 if (fpga->info)
177 fpga->info(desc);
wdenk9b7f3842003-10-09 20:09:04 +0000178 } else {
Marek Vasut18221352014-09-16 20:29:24 +0200179 printf("No Device Function Table.\n");
wdenk9b7f3842003-10-09 20:09:04 +0000180 }
181
Marek Vasutf5d25e42014-09-16 21:17:51 +0200182 return FPGA_SUCCESS;
wdenk9b7f3842003-10-09 20:09:04 +0000183}